Pipeline Interlock on Data Hazard

In pipelined microprocessors, a Read-After-Write (RAW) data hazard occurs when an instruction requires a register value that is still being computed by an older instruction in flight. The simplest hardware resolution is an interlock mechanism that freezes the early stages of the pipeline until the required data reaches the writeback stage.

This module monitors a hazard detection flag from the decode stage. When a hazard is detected, it must immediately assert a stall signal to freeze the fetch and decode stages, and assert a bubble signal to insert a NOP into the execute stage. Because the data takes two additional clock cycles to reach the writeback stage, the stall and bubble signals must remain asserted for exactly two consecutive cycles. During the second cycle of the stall, the pipeline is already frozen, so any hazard detection inputs must be ignored.

Timing and Reset Rules: • Clock edge: posedge clk • Reset: Asynchronous, active-low (rst_n) • Reset values: stall and bubble default to 0; internal state resets to idle. • Outputs stall and bubble must react combinationally in the exact same cycle that hazard_detected is asserted. • The second cycle of the stall is driven by internal sequential logic.

Worked Trace: • Cycle 1: rst_n=0 → stall=0, bubble=0 • Cycle 2: rst_n=1, hazard_detected=0 → stall=0, bubble=0 • Cycle 3: hazard_detected=1 → stall=1, bubble=1 (Cycle 1 of stall) • Cycle 4: hazard_detected=1 (ignored) → stall=1, bubble=1 (Cycle 2 of stall) • Cycle 5: hazard_detected=0 → stall=0, bubble=0 (Stall complete) • Cycle 6: hazard_detected=1 → stall=1, bubble=1 (Cycle 1 of new stall) • Cycle 7: hazard_detected=0 → stall=1, bubble=1 (Cycle 2 of new stall) • Cycle 8: hazard_detected=0 → stall=0, bubble=0

{ "signal": [
  { "name": "clk",             "wave": "p......." },
  { "name": "rst_n",           "wave": "01......" },
  { "name": "hazard_detected", "wave": "00110100" },
  {},
  { "name": "stall",           "wave": "00110110" },
  { "name": "bubble",          "wave": "00110110" }
], "head": { "text": "A 2-cycle interlock reacting combinationally to hazard_detected." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; outputs go to 0 | | hazard_detected | input | 1 | Asserted when a RAW hazard is identified | | stall | output | 1 | Freezes the early pipeline stages | | bubble | output | 1 | Inserts a NOP into the later pipeline stages |

Constraints

• Clock edge: posedge clk
• Reset: Asynchronous, active-low (rst_n)
• Outputs stall and bubble must be combinational with respect to hazard_detected to stall the pipeline in the current cycle.
• The stall must last exactly two clock cycles per hazard event.
• If hazard_detected is asserted during the second cycle of an ongoing stall, it must be ignored.
• Outputs stall and bubble must be 0 on reset.

Topics

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