Registered vs Combinational Output

Network packet parsers and serial interfaces often suffer from timing violations when combinational logic paths become too long. Mealy state machines, which compute outputs based on both the current state and immediate inputs, are particularly prone to generating glitches that propagate to downstream modules. Registering these outputs guarantees clean and glitch free signals with predictable timing, at the cost of one clock cycle of latency.

This module implements an overlapping sequence detector that searches for the pattern consisting of two consecutive ones on a serial input line. It provides two distinct detection flags to illustrate output timing differences. The combinational flag asserts immediately as soon as the second one is present at the input while the machine is in the correct state. The registered flag asserts one clock cycle later, capturing the combinational flag's state into a dedicated flip flop.

Timing and Reset Rules

• Clock edge: posedge clk
• Reset type: asynchronous active low rst_n
• Output values on reset: detect_reg must be 0; the internal state machine must return to the IDLE state, meaning detect_comb must also evaluate to 0
• Priority rules: Reset has the highest priority and takes effect immediately, regardless of the clock
• State encoding: Use 0 for IDLE (waiting for the first 1) and 1 for SEEN_1 (waiting for the second 1)
• Overlapping behaviour: The sequence of three consecutive ones must trigger the detection flags twice

Worked Trace

Combinational Mealy outputs evaluate at the end of the clock cycle, just before the next positive edge.

Cycle 1: rst_n=0, din=0 → state=IDLE, detect_comb=0, detect_reg=0 Cycle 2: rst_n=1, din=1 → state=IDLE, detect_comb=0, detect_reg=0 Cycle 3: rst_n=1, din=1 → state=SEEN_1, detect_comb=1, detect_reg=0 Cycle 4: rst_n=1, din=1 → state=SEEN_1, detect_comb=1, detect_reg=1 Cycle 5: rst_n=1, din=0 → state=SEEN_1, detect_comb=0, detect_reg=1 Cycle 6: rst_n=1, din=0 → state=IDLE, detect_comb=0, detect_reg=0

State Diagram

flowchart LR
    RESET(( )) -->|reset| IDLE
    IDLE((IDLE)) -->|din=1| SEEN_1
    IDLE -->|din=0| IDLE
    SEEN_1(["SEEN_1 ★"]):::out -->|din=1 / comb=1| SEEN_1
    SEEN_1 -->|din=0| IDLE
    classDef out fill:#6C5CE7,stroke:#5B4FE8,color:#fff

Timing Diagram

{ "signal": [
  { "name": "clk",         "wave": "p......" },
  { "name": "rst_n",       "wave": "01....." },
  { "name": "din",         "wave": "01..0.." },
  {},
  { "name": "state",       "wave": "2.2..2.", "data": ["IDLE", "SEEN_1", "IDLE"] },
  { "name": "detect_comb", "wave": "0.1.0.." },
  { "name": "detect_reg",  "wave": "0..1.0." }
], "head": { "text": "Cycle level comparison of combinational versus registered outputs." } }

Port Table

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive edge triggered clock | | rst_n | input | 1 | Asynchronous active low reset; all registers go to 0 when asserted | | din | input | 1 | Serial data input | | detect_comb | output | 1 | Combinational Mealy output; goes high immediately when state is SEEN_1 and din is 1 | | detect_reg | output | 1 | Registered output; captures the value of detect_comb on the posedge of clk |

Constraints

• The design must trigger on posedge clk and reset on negedge rst_n
• detect_reg must be strictly 0 upon reset
• The FSM must support overlapping sequences without returning to IDLE
• detect_comb must be purely combinational and respond to din changes in the exact same clock cycle
• detect_reg must be a registered version of detect_comb, introducing exactly one clock cycle of latency

Topics

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