Synchronous Active High Reset
Modern FPGA architectures map logic most efficiently when designs use synchronous active-high resets. This aligns with the underlying hardware of DSP slices and block RAMs, allowing synthesis tools to pack logic densely.
A standard D flip-flop captures an 8-bit data input on the rising edge of the clock. When the reset signal is asserted during a rising clock edge, the output is forced to zero regardless of the data input.
Clock edge: posedge Reset type: Synchronous Reset polarity: Active-high Output values on reset: q becomes 8'h00 Priority rules: rst has priority over d when both are asserted simultaneously.
Cycle 1: rst=1, d=8'hAA → q=8'h00 (synchronous reset overrides data) Cycle 2: rst=0, d=8'h55 → q=8'h55 (normal operation) Cycle 3: rst=0, d=8'hFF → q=8'hFF (normal operation) Cycle 4: rst=1, d=8'h12 → q=8'h00 (synchronous reset overrides data) Cycle 5: rst=0, d=8'h34 → q=8'h34 (normal operation)
{ "signal": [
{ "name": "clk", "wave": "p....." },
{ "name": "rst", "wave": "10..10" },
{ "name": "d", "wave": "======", "data": ["AA", "55", "FF", "12", "34", "56"] },
{},
{ "name": "q", "wave": "x=====", "data": ["00", "55", "FF", "00", "34"] }
], "head": { "text": "Cycle-by-cycle synchronous reset behavior." } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst | input | 1 | Synchronous active-high reset; forces q to 0 when asserted | | d | input | 8 | Data input | | q | output | 8 | Registered data output; resets to 8'h00 |
Constraints
- Clock edge must be
posedge - Reset must be synchronous and active-high
rstmust have priority overdqmust be a registered outputrstmust NOT be included in the sensitivity list of thealwaysblock
Topics
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