Up Down Counter with Dynamic Step

Hardware performance monitors and packet queue trackers frequently require counters that can adjust by variable amounts in both directions. The solution module is an 8-bit counter that can add or subtract a dynamic step size on every clock cycle. To optimize for synthesis and ensure the tool infers a single adder rather than separate addition and subtraction logic blocks, the design must compute the next value by conditionally converting the step size to its two's complement form before adding it to the current count.

The module maintains an 8-bit count. On a positive clock edge, if enabled, it increments the count by the step input when down is 0. If down is 1, it decrements the count by the step input. If not enabled, the count remains unchanged. The counter wraps naturally on overflow and underflow boundaries.

• Clock edge: posedge clk
• Reset type: Asynchronous
• Reset polarity: Active-low (rst_n)
• Output on reset: count goes to 8'b0000_0000
• Priority rules: Reset has highest priority. en must be 1 for step and down to affect the count.

Cycle 1: rst_n=0 → count=0 Cycle 2: rst_n=1, en=1, down=0, step=5 → count=5 Cycle 3: en=1, down=0, step=3 → count=8 Cycle 4: en=1, down=1, step=2 → count=6 Cycle 5: en=0, down=1, step=10 → count=6 (hold)

{ "signal": [
  { "name": "clk",   "wave": "p....." },
  { "name": "rst_n", "wave": "01...." },
  { "name": "en",    "wave": "x1.10." },
  { "name": "down",  "wave": "x0.1.." },
  { "name": "step",  "wave": "x====.", "data": ["5", "3", "2", "10"] },
  {},
  { "name": "count", "wave": "=.====", "data": ["0", "5", "8", "6", "6"] }
], "head": { "text": "Counter increments and decrements by dynamic step sizes." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n| input | 1 | Asynchronous active-low reset; count goes to 0 | | en | input | 1 | Enable signal; updates count when 1 | | down | input | 1 | Direction control; 0 for add, 1 for subtract | | step | input | 8 | Dynamic step size to add or subtract | | count| output | 8 | Current counter value |

Constraints

• Clock edge is posedge clk and reset is asynchronous active-low.
• count must initialize to 8'b0000_0000 on reset.
• Reset has priority over en.
• Counter must wrap around naturally on overflow and underflow boundaries.
• All outputs are registered.

Topics

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