4-Bit Ripple Binary Counter from T Flip-Flops
Low-power frequency dividers and simple timing circuits often rely on asynchronous counting structures. A 4-bit ripple binary counter divides an input clock frequency by up to sixteen, utilizing cascaded toggle stages rather than a globally distributed clock network.
The circuit must increment its 4-bit value Q3, Q2, Q1, Q0 on each falling edge of the main CLK. The least significant bit Q0 toggles on the primary clock. Each subsequent bit toggles on the falling edge of the preceding stage's output. The RST signal asynchronously clears all outputs to 0.
| RST | CLK | Q3 | Q2 | Q1 | Q0 | |-------|-------|------|------|------|------| | 1 | X | 0 | 0 | 0 | 0 | | 0 | fall | 0 | 0 | 0 | 1 | | 0 | fall | 0 | 0 | 1 | 0 | | 0 | fall | 0 | 0 | 1 | 1 | | 0 | fall | 0 | 1 | 0 | 0 |
Constraints
- Use exactly four falling-edge triggered T flip-flops.
- Tie the
Tinput of all flip-flops permanently to logic 1. - Connect the main
CLKsignal only to the clock input of the first flip-flop. - Drive the clock input of each subsequent flip-flop using the
Qoutput of the preceding stage.
Topics
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