Active Low Reset Polarity Mismatch
A 1-bit register with an active-low asynchronous reset ensures the system starts in a known zero state.
Expected behavior:
| rst_n | clk | D | Q | |---------|-------|-----|-----| | 0 | X | X | 0 | | 1 | 0 | X | Holds state | | 1 | ↑ | 0 | 0 | | 1 | ↑ | 1 | 1 |
Simulation shows Q = 0 when rst_n = 1, clk = 1, and D = 1. The register fails to latch the input data during normal operation. Additionally, asserting rst_n = 0 fails to clear the register if it was previously set. Inspect the circuit and correct the fault.
Constraints
- Do not modify the input or output pins.
- The circuit must resolve the polarity mismatch using standard logic gates or by replacing the flip-flop component.
Topics
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