Asynchronous FIFO Overflow Due to Delayed Flag
An asynchronous FIFO safely passes data between unrelated clock domains using Gray-coded pointers.
Expected behavior:
The full flag must assert immediately when the next write pointer equals the synchronized read pointer with the top two bits inverted. This pessimistic evaluation ensures no writes occur when the FIFO lacks capacity.
Simulation shows data corruption during a burst write sequence. The testbench reports dropped words because the FIFO accepts a write while at capacity. The full flag outputs 0 when the 4-bit Gray-coded write pointer reaches w3=1, w2=1, w1=0, w0=0 and the synchronized read pointer is r3=0, r2=0, r1=0, r0=0.
Inspect the circuit and correct the fault.
Constraints
- Do not change the input or output port names.
- The circuit must use combinational logic to evaluate the pointers in a single cycle.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.