Basic Interface Grouping

EasyVerilog / SystemVerilogBuild

Complex System-on-Chip designs often route dozens of signals between controllers and peripherals. Module port lists with fifty distinct wires are unmaintainable and highly prone to connection errors. SystemVerilog solves this by bundling related signals into an interface block, allowing an entire bus to be passed through a single module port.

The internal logic for this problem acts as a status register and loopback for an SPI peripheral. It reads inputs from a grouped interface and drives outputs back to the interface based on a system clock and an active-low reset. When the module is enabled, it captures the transmitted data, echoes the serial input, flags whether the chip select is active, asserts a ready signal, and detects a specific error state. When disabled, all outputs maintain their previous values.

Clock edge: clk is positive-edge triggered.
Reset: rst_n is an asynchronous active-low reset. When rst_n is 0, all outputs (miso, tx_ready, rx_data, rx_valid, error) are driven to 0.
Logic behavior: On the positive edge of clk, if rst_n is 1 and enable is 1:
miso takes the value of mosi.
rx_data takes the value of tx_data.
rx_valid is set to 1 if cs_n is 0, otherwise 0.
tx_ready is permanently set to 1.
error is set to 1 if mosi is 1 while cs_n is 1, otherwise 0.
If enable is 0, all outputs hold their current state.

The student must define an interface named spi_if containing the 12 signals below, and a module solution that takes a single port named bus of type spi_if.

| Signal | Direction (Logical) | Width | Description | |--------|---------------------|-------|-------------| | clk | Input to module | 1 | Positive-edge triggered system clock | | rst_n | Input to module | 1 | Asynchronous active-low reset | | sclk | Input to module | 1 | SPI clock (unused in logic, but required in interface) | | cs_n | Input to module | 1 | Active-low chip select | | mosi | Input to module | 1 | Master-out slave-in serial data | | miso | Output from module| 1 | Master-in slave-out serial data | | tx_data | Input to module | 8 | Parallel data to transmit | | tx_ready| Output from module| 1 | Transmitter ready flag | | rx_data | Output from module| 8 | Parallel data received | | rx_valid| Output from module| 1 | Receiver valid flag | | error | Output from module| 1 | Protocol error flag | | enable | Input to module | 1 | Module enable flag |

Cycle 1: rst_n=0 → miso=0, rx_data=0, rx_valid=0, tx_ready=0, error=0 Cycle 2: rst_n=1, enable=1, cs_n=0, mosi=1, tx_data=8'hAA → miso=1, rx_data=8'hAA, rx_valid=1, tx_ready=1, error=0 Cycle 3: enable=0, cs_n=1, mosi=0, tx_data=8'hBB → miso=1, rx_data=8'hAA, rx_valid=1, tx_ready=1, error=0 (hold) Cycle 4: enable=1, cs_n=1, mosi=1, tx_data=8'h11 → miso=1, rx_data=8'h11, rx_valid=0, tx_ready=1, error=1

{ "signal": [
  { "name": "clk", "wave": "p...." },
  { "name": "rst_n", "wave": "01..." },
  { "name": "enable", "wave": "0101." },
  { "name": "cs_n", "wave": "1011." },
  { "name": "mosi", "wave": "0101." },
  { "name": "tx_data", "wave": "===== ", "data": ["00", "AA", "BB", "11", "11"] },
  {},
  { "name": "miso", "wave": "01.1." },
  { "name": "rx_data", "wave": "===== ", "data": ["00", "AA", "AA", "11", "11"] },
  { "name": "rx_valid", "wave": "01.0." },
  { "name": "tx_ready", "wave": "01..." },
  { "name": "error", "wave": "0..1." }
], "head": { "text": "Cycle 1: Reset. Cycle 2: Enable active. Cycle 3: Hold state. Cycle 4: Error condition detected." } }

Constraints

The interface must be named exactly spi_if.
The module must be named exactly solution.
The module must have exactly one port named bus of type spi_if.
All signals inside the interface must be declared as logic.
Do not use modport declarations for this exercise.
All assignments to the interface outputs must be synchronous to the positive edge of clk or the negative edge of rst_n.

Topics

Best PracticesSystemVerilogInterfaces

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