Baud Rate Pulse Generator

Every UART transmitter needs a mechanism to pace its bit output to the receiver's baud rate. State machines must run on the fast system clock, but they should only change state when a baud tick occurs. Generating a divided clock directly introduces dangerous clock domain crossing issues; instead, synchronous designs use a single-cycle enable pulse that acts as a clock enable for the downstream logic.

The solution module takes a 16-bit baud_limit input representing the number of system clock cycles per baud period. It counts system clock cycles internally. When the internal counter reaches baud_limit - 1, it asserts the tick output for exactly one clock cycle and resets the counter to zero on the next clock edge.

Clock edge and reset rules: • Clock edge: posedge clk • Reset type: asynchronous • Reset polarity: active-low rst_n • Output values on reset: tick is 0, and the internal counter resets to 0

Worked trace for baud_limit = 3: Cycle 1: rst_n=0, baud_limit=3 → count=0, tick=0 Cycle 2: rst_n=1, posedge clk → count=1, tick=0 Cycle 3: rst_n=1, posedge clk → count=2, tick=1 Cycle 4: rst_n=1, posedge clk → count=0, tick=0 Cycle 5: rst_n=1, posedge clk → count=1, tick=0 Cycle 6: rst_n=1, posedge clk → count=2, tick=1

{ "signal": [
  { "name": "clk", "wave": "p......" },
  { "name": "rst_n", "wave": "01....." },
  { "name": "baud_limit", "wave": "2......", "data": ["3"] },
  {},
  { "name": "count (internal)", "wave": "222222.", "data": ["0","1","2","0","1","2"] },
  { "name": "tick", "wave": "001001." }
], "head": { "text": "Baud tick generation for baud_limit = 3." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered system clock | | rst_n | input | 1 | Asynchronous active-low reset; counter and tick go to 0 | | baud_limit | input | 16 | Number of clock cycles per baud period (always ≥ 2) | | tick | output | 1 | Single-cycle pulse asserted when counter reaches baud_limit - 1 |

Constraints

• The clk input is positive-edge triggered and rst_n is asynchronous active-low.
• The tick output must be 0 when rst_n is asserted.
• The internal counter must be 16 bits wide to support large baud_limit values up to 16'hFFFF.
• The baud_limit input is guaranteed to be stable and ≥ 2 during operation.
• The tick output is a combinational signal that evaluates to 1 during the clock cycle where the internal counter equals baud_limit - 1.

Topics

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