UART Transmitter FSM

MediumVerilog / SystemVerilogBuild

Every digital System on Chip relies on a UART transmitter as its primary debug interface to serialize bytes over a single wire to a host terminal.

The transmitter accepts an 8-bit parallel data word using a standard valid and ready handshake. Once accepted, it serializes the data into a standard 10-bit UART frame consisting of a start bit (0), eight data bits transmitted Least Significant Bit (LSB) first, and a stop bit (1). The shifting of bits out onto the serial line is paced entirely by a single-cycle baud enable pulse, which asserts at the target baud rate.

The module is driven by a positive-edge triggered clock clk and an asynchronous active-low reset rst_n. On reset, the serial output tx must idle high (1), and the transmitter must be ready to accept new data (ready = 1). When valid and ready are both 1 on a clock edge, the input byte is captured. The start bit is transmitted on the first baud_en pulse following the capture. The ready signal remains low (0) until the stop bit has been fully transmitted and held for one complete baud_en cycle.

Cycle 1: rst_n=0 → ready=1, tx=1 Cycle 2: rst_n=1, valid=1, data=8'hA5, baud_en=0 → ready=1, tx=1 (handshake occurs) Cycle 3: valid=0, baud_en=1 → ready=0, tx=0 (start bit) Cycle 4: baud_en=0 → ready=0, tx=0 (hold start bit) Cycle 5: baud_en=1 → ready=0, tx=1 (data bit 0) Cycle 6: baud_en=1 → ready=0, tx=0 (data bit 1) Cycle 7: baud_en=1 → ready=0, tx=1 (data bit 2) Cycle 8: baud_en=1 → ready=0, tx=0 (data bit 3) Cycle 9: baud_en=1 → ready=0, tx=0 (data bit 4) Cycle 10: baud_en=1 → ready=0, tx=1 (data bit 5) Cycle 11: baud_en=1 → ready=0, tx=0 (data bit 6) Cycle 12: baud_en=1 → ready=0, tx=1 (data bit 7) Cycle 13: baud_en=1 → ready=0, tx=1 (stop bit) Cycle 14: baud_en=1 → ready=1, tx=1 (return to idle)

flowchart LR
    RESET(( )) -->|reset| IDLE
    IDLE((IDLE)) -->|valid=1| START
    IDLE -->|valid=0| IDLE
    START(["START ★"]):::out -->|baud_en=1| DATA
    START -->|baud_en=0| START
    DATA(["DATA ★"]):::out -->|baud_en=1 & bit=7| STOP
    DATA -->|otherwise| DATA
    STOP(["STOP ★"]):::out -->|baud_en=1| IDLE
    STOP -->|baud_en=0| STOP
    classDef out fill:#6C5CE7,stroke:#5B4FE8,color:#fff

{ "signal": [
  { "name": "clk", "wave": "p............." },
  { "name": "rst_n", "wave": "01............" },
  { "name": "valid", "wave": "010..........." },
  { "name": "data", "wave": "x=x...........", "data": ["8'hA5"] },
  { "name": "baud_en", "wave": "00101111111111" },
  { "name": "ready", "wave": "11000000000001" },
  { "name": "tx", "wave": "11001010010111" }
], "head": { "text": "UART transmission of 8'hA5 (10100101) LSB first." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; tx and ready go to 1 when asserted | | baud_en | input | 1 | Baud enable pulse; shifts the FSM state and serializes data when 1 | | valid | input | 1 | Valid data indicator; combined with ready to capture data | | data | input | 8 | The 8-bit data byte to be serialized | | ready | output | 1 | Ready indicator; 1 when idle, 0 during transmission | | tx | output | 1 | Serial output; idles at 1, drops to 0 for start bit |

Constraints

Positive-edge triggered clock clk.
Asynchronous active-low reset rst_n.
On reset, tx must be 1 and ready must be 1.
The data byte is captured on the clock edge where valid and ready are both 1.
State transitions and tx updates must only occur when baud_en is 1, except for capturing data which occurs regardless of baud_en.
The ready signal must remain 0 until the stop bit has been fully transmitted and held for one full baud_en cycle.
Data is transmitted Least Significant Bit (LSB) first.

Topics

FSMShift RegisterUARTProtocol

Solve this problem

Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.

This problem is part of Codiode Pro. The statement above is free to read.

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

Constraints

Positive-edge triggered clock clk.
Asynchronous active-low reset rst_n.
On reset, tx must be 1 and ready must be 1.
The data byte is captured on the clock edge where valid and ready are both 1.
State transitions and tx updates must only occur when baud_en is 1, except for capturing data which occurs regardless of baud_en.
The ready signal must remain 0 until the stop bit has been fully transmitted and held for one full baud_en cycle.
Data is transmitted Least Significant Bit (LSB) first.

Topics

FSMShift RegisterUARTProtocol

Solve this problem

Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.

This problem is part of Codiode Pro. The statement above is free to read.

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

UART Transmitter FSM

Constraints

Topics

Solve this problem

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UART Transmitter FSM

Constraints

Topics

Solve this problem

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