UART Receiver Oversampling Counter

Asynchronous serial communication requires receivers to recover the transmitter's clock timing from the data stream itself. UART receivers achieve this by oversampling the incoming data line, typically at sixteen times the baud rate, to find the center of the start bit and align subsequent sampling.

The module monitors the rx line while rx_active is asserted. It must detect a falling edge (a transition from 1 to 0) on rx to identify the start of a transmission. Once a falling edge is detected, it waits exactly 8 clock cycles to reach the middle of the start bit. If rx is still 0 at this point, it asserts the sample output for one clock cycle and transitions to continuous sampling, asserting sample every 16 clock cycles thereafter. If rx is 1 at the 8th cycle, it assumes the initial drop was a glitch and returns to monitoring for a new falling edge. If rx_active is deasserted, the module resets its internal state immediately.

### Timing and Reset The module operates on the positive edge of clk. It uses an asynchronous active-low reset rst_n. On reset, the sample output and all internal state must go to 0.

### Worked Trace Cycle 1: rst_n=1, rx_active=1, rx=1 → Idle state. Cycle 2: rx=0 → Falling edge detected, begin half-bit wait. Cycle 3 to 8: Counting up to 7. Cycle 9: 8th cycle reached, rx=0 → sample=1, begin full-bit wait. Cycle 10 to 24: Counting 15 cycles. Cycle 25: 16th cycle reached → sample=1.

Port Table

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; all outputs go to 0 when asserted | | rx | input | 1 | Asynchronous serial data line | | rx_active | input | 1 | Enable signal; module operates when 1, resets state when 0 | | sample | output | 1 | Pulses high for 1 cycle at the center of each bit |

Constraints

• clk is positive-edge triggered and rst_n is asynchronous active-low.
• sample must be a registered output and initialize to 0.
• The start bit is identified by a 1-to-0 transition on rx. If rx is already 0 when rx_active is asserted, the module must wait for rx to return to 1 and then drop to 0 before starting.
• The previous rx state for edge detection must be assumed to be 1 upon reset.
• If rx_active goes to 0, all internal counters and state must reset immediately.
• The first sample pulse occurs exactly 8 clock cycles after the falling edge is detected. Subsequent pulses occur exactly every 16 clock cycles.

Topics

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