Branch Flush Mechanism

High-performance CPUs execute instructions speculatively to keep their pipelines full. When a control decision (like a branch instruction) evaluates differently than predicted, the pipeline contains invalid speculative instructions that must be destroyed before they commit their state. This module models a simplified 3-stage instruction pipeline where invalidation happens via an asynchronous flush signal.

The pipeline consists of three stages. Each stage holds an 8-bit instruction payload and a 1-bit valid flag. During normal operation, instructions and their valid bits propagate from Stage 1 to Stage 3 on each clock cycle. When a branch mispredict is detected, the flush signal is asserted. This must immediately and asynchronously clear the valid bits of Stage 1 and Stage 2 to 0. However, Stage 3 represents an instruction older than the branch, so its valid bit must be allowed to complete normally and is unaffected by the flush. Data payloads continue to propagate through all stages on every clock cycle regardless of the flush signal or valid bits.

Timing and Reset Rules: • Clock: clk is positive-edge triggered. • Reset: rst_n is an asynchronous, active-low reset. When asserted, all valid bits and data payloads across all three stages must be cleared to 0. • Flush: flush is an asynchronous, active-high signal. When asserted, it immediately forces the valid bits of Stage 1 and Stage 2 to 0. It does not affect the data payloads, nor does it affect Stage 3. • Priority: rst_n has priority over flush.

Worked Trace: Cycle 1: rst_n=0 → S1=(0,0), S2=(0,0), S3=(0,0), out_valid=0, out_data=0 Cycle 2: rst_n=1, in_valid=1, in_data=11 → S1=(1,11), S2=(0,0), S3=(0,0), out_valid=0, out_data=0 Cycle 3: in_valid=1, in_data=22 → S1=(1,22), S2=(1,11), S3=(0,0), out_valid=0, out_data=0 Cycle 4: in_valid=1, in_data=33 → S1=(1,33), S2=(1,22), S3=(1,11), out_valid=1, out_data=11 Mid-Cycle 4.5: flush=1 → S1=(0,33), S2=(0,22), S3=(1,11) (valid bits clear asynchronously) Cycle 5: flush=0, in_valid=1, in_data=44 → S1=(1,44), S2=(0,33), S3=(0,22), out_valid=0, out_data=22

{ "signal": [
  { "name": "clk",       "wave": "p......" },
  { "name": "rst_n",     "wave": "01....." },
  { "name": "flush",     "wave": "0...10." },
  { "name": "in_valid",  "wave": "01....." },
  { "name": "in_data",   "wave": "x======", "data": ["11","22","33","44","55","66"] },
  {},
  { "name": "out_valid", "wave": "0...10." },
  { "name": "out_data",  "wave": "x...===", "data": ["11","22","33"] }
], "head": { "text": "Pipeline flow with an asynchronous flush clearing Stage 1 and Stage 2 mid-cycle." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; clears all valid bits and data to 0 | | flush | input | 1 | Asynchronous active-high flush; clears Stage 1 and Stage 2 valid bits to 0 immediately | | in_valid | input | 1 | Input valid signal for Stage 1 | | in_data | input | 8 | Input instruction payload for Stage 1 | | out_valid | output | 1 | Output valid signal from Stage 3 | | out_data | output | 8 | Output instruction payload from Stage 3 |

Constraints

• The flush signal must act asynchronously on the valid bits of Stage 1 and Stage 2.
• The flush signal must NOT asynchronously clear the data payloads of any stage, nor the valid bit of Stage 3.
• Data payloads must continue to propagate synchronously through the pipeline regardless of the valid bits or the flush signal.
• All registers (both valid and data) must be cleared to 0 when rst_n is 0.

Topics

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