Simultaneous Stall and Flush Priority

High-performance microprocessors rely on precise pipeline control to manage instruction flow. When a branch misprediction occurs, the pipeline must be flushed to discard speculative instructions. Simultaneously, data hazards might assert a global stall signal. If control logic does not explicitly define priority between these events, a stalled speculative instruction might survive a flush and corrupt architectural state.

The module tracks the validity of instructions across a 4-stage pipeline. Under normal operation, the input valid signal shifts into the first stage (bit 0), and existing valid bits propagate to subsequent stages (shifted left towards bit 3) on each clock cycle. When a stall is asserted, the pipeline freezes, holding its current valid state and ignoring the input. When a flush is asserted, all pipeline stages are immediately invalidated on the next clock edge. If both stall and flush are asserted on the same cycle, the flush must override the stall to ensure the pipeline is safely cleared.

• Clock edge: posedge clk
• Reset type: Asynchronous, active-low (rst_n)
• Output reset value: valid_stages goes to 4'b0000
• Priority: flush > stall > normal operation
• All outputs are registered

Cycle 1: rst_n=0 → valid_stages=4'b0000 Cycle 2: rst_n=1, valid_in=1, stall=0, flush=0 → valid_stages=4'b0001 Cycle 3: valid_in=1, stall=0, flush=0 → valid_stages=4'b0011 Cycle 4: valid_in=0, stall=1, flush=0 → valid_stages=4'b0011 (hold due to stall) Cycle 5: valid_in=1, stall=1, flush=1 → valid_stages=4'b0000 (flush overrides stall) Cycle 6: valid_in=1, stall=0, flush=0 → valid_stages=4'b0001 (recovery)

{ "signal": [
  { "name": "clk", "wave": "p......" },
  { "name": "rst_n", "wave": "01....." },
  { "name": "valid_in", "wave": "x1.01.." },
  { "name": "stall", "wave": "0..1.0." },
  { "name": "flush", "wave": "0...10." },
  {},
  { "name": "valid_stages", "wave": "=.====.", "data": ["0000", "0001", "0011", "0011", "0000", "0001"] }
], "head": { "text": "Pipeline valid bit tracking with flush overriding stall." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; clears all valid bits to 0 | | valid_in | input | 1 | Incoming valid bit for the first pipeline stage | | stall | input | 1 | Freezes the pipeline state when asserted | | flush | input | 1 | Clears all valid bits to 0 when asserted | | valid_stages | output | 4 | Registered valid bits for pipeline stages 1 through 4 (bits 0 to 3) |

Constraints

• The reset must be asynchronous and active-low
• The valid_stages output must be updated only on the positive edge of clk or the negative edge of rst_n
• When flush and stall are both 1, the pipeline must clear to 4'b0000
• The shift direction must move data from bit 0 (stage 1) towards bit 3 (stage 4)

Topics

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