Parameterized Pipeline Delay Line

High-speed digital systems frequently require signals to be delayed by a fixed number of clock cycles to align data paths, such as matching the latency of a parallel arithmetic pipeline. Hardcoding individual flip-flops for these delay lines does not scale and leads to rigid, non-reusable code. A parameterized delay line allows a single module to serve as an N-stage shift register across an entire system, adjusting automatically to the required depth.

The module captures an incoming data vector and delays it by a configurable number of clock cycles specified by the parameter DEPTH. Data advances through the pipeline only when the enable signal is asserted. When the enable signal is de-asserted, all stages in the pipeline hold their current values.

The circuit must be driven by a positive-edge triggered clock clk. An asynchronous, active-low reset rst_n clears all pipeline stages to zero immediately when asserted. The output data_out reflects the value of the final pipeline stage.

Worked trace for a pipeline with DEPTH=3: • Cycle 1: rst_n=0, en=1, data_in=8'hAA, pipeline=[0, 0, 0], data_out=0 • Cycle 2: rst_n=1, en=1, data_in=8'hAA, (posedge clk) pipeline=[8'hAA, 0, 0], data_out=0 • Cycle 3: rst_n=1, en=1, data_in=8'hBB, (posedge clk) pipeline=[8'hBB, 8'hAA, 0], data_out=0 • Cycle 4: rst_n=1, en=1, data_in=8'hCC, (posedge clk) pipeline=[8'hCC, 8'hBB, 8'hAA], data_out updates to 8'hAA • Cycle 5: rst_n=1, en=0, data_in=8'hDD, (posedge clk) pipeline holds, data_out remains 8'hAA • Cycle 6: rst_n=1, en=1, data_in=8'hDD, (posedge clk) pipeline=[8'hDD, 8'hCC, 8'hBB], data_out updates to 8'hBB

{ "signal": [
  { "name": "clk",      "wave": "p......." },
  { "name": "rst_n",    "wave": "01......" },
  { "name": "en",       "wave": "x1..01.." },
  { "name": "data_in",  "wave": "x======.", "data": ["AA", "BB", "CC", "DD", "DD", "EE"] },
  {},
  { "name": "data_out", "wave": "=====.=.", "data": ["00", "00", "00", "00", "AA", "BB"] }
], "head": { "text": "3-stage delay line (DEPTH=3) propagation and enable hold." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; clears all stages to 0 | | en | input | 1 | Clock enable; pipeline advances on posedge clk when 1 | | data_in | input | WIDTH | Input data vector to be delayed | | data_out | output | WIDTH | Delayed data vector from the final pipeline stage |

Constraints

• The parameter WIDTH defaults to 8 and is guaranteed to be >= 1.
• The parameter DEPTH defaults to 4 and is guaranteed to be >= 1.
• The output data_out must be registered and update synchronously on the positive edge of clk.
• When en is 0, all internal stages must perfectly hold their previous state.

Topics

Related problems

• Basic D Flip FlopEasy
• Debug: Missing Edge in Sensitivity ListMedium
• Read After Write Hazard DetectionEasy
• Parameterized Interface with ModportsHard
• Struct Array PipelineHard
• T Flip Flop from D Flip Flop TemplateEasy
• Recursive Generate Reduction TreeHard
• Four Stage Shift RegisterEasy