Parameterized Pipeline with Valid Signals
High-speed digital designs frequently employ parameterized pipelines to meet timing closure, requiring both datapath and control signals to propagate in lockstep. If a control signal arrives at a destination before its corresponding data, the system will process invalid information and corrupt the state.
The solution module acts as a parameterized delay line. It receives a WIDTH-bit data signal and an accompanying valid_in flag. Both signals must be delayed by exactly DEPTH clock cycles. When valid_in is asserted, the data enters the pipeline. Exactly DEPTH cycles later, valid_out asserts with the corresponding data_out.
Timing and Reset Rules: • Clock edge: posedge clk • Reset type: Asynchronous • Reset polarity: Active-low (rst_n) • Output values on reset: All valid bits and data registers across all pipeline stages must be immediately cleared to 0. • Output type: valid_out and data_out represent the final registered stage of the pipeline.
Worked Trace (DEPTH=4): Cycle 1: rst_n=0 → valid_out=0, data_out=8'h00 (pipeline empty) Cycle 2: rst_n=1, valid_in=1, data_in=8'hAA → data enters stage 1; valid_out=0 Cycle 3: valid_in=0, data_in=8'h00 → data moves to stage 2; valid_out=0 Cycle 4: valid_in=1, data_in=8'hBB → data moves to stage 3, 8'hBB enters stage 1; valid_out=0 Cycle 5: valid_in=0 → data moves to stage 4 (output); valid_out=1, data_out=8'hAA Cycle 6: valid_in=0 → 8'hBB moves to stage 3; valid_out=0, data_out=8'h00 Cycle 7: valid_in=0 → 8'hBB moves to stage 4 (output); valid_out=1, data_out=8'hBB Cycle 8: valid_in=0 → pipeline flushes; valid_out=0, data_out=8'h00
{ "signal": [
{ "name": "clk", "wave": "p......." },
{ "name": "rst_n", "wave": "01......" },
{ "name": "valid_in", "wave": "01010000" },
{ "name": "data_in", "wave": "x=x=xxxx", "data": ["AA", "BB"] },
{ "name": "valid_out", "wave": "0...1010" },
{ "name": "data_out", "wave": "0...=x=x", "data": ["AA", "BB"] }
], "head": { "text": "Pipeline behavior with DEPTH=4" } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; clears all pipeline stages to 0 | | valid_in | input | 1 | Indicates data_in is valid | | data_in | input | WIDTH | Input data to be pipelined | | valid_out | output | 1 | Delayed valid signal | | data_out | output | WIDTH | Delayed data signal |
Constraints
WIDTHandDEPTHare strictly positive integers (DEPTH >= 1,WIDTH >= 1).- On reset, every register in every pipeline stage must be cleared to 0.
- Both the datapath and the valid flag must be delayed by exactly
DEPTHcycles. - The module outputs must be driven directly by the final register stage.
Topics
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