Clock Divider Phase Ambiguity
Dual clock dividers generate localized slow clocks for different modules on a synchronous chip. A master clock feeds two identical divide-by-4 circuits to produce Clk_out1 and Clk_out2.
Expected behavior:
Both dividers must come out of reset simultaneously to guarantee zero phase difference between Clk_out1 and Clk_out2. When Rst is 1, both outputs are 0. When Rst transitions to 0, both outputs act as 50 percent duty cycle clocks running at one quarter the frequency of the master clock. They must rise and fall in perfect unison.
Simulation shows Clk_out2 transitioning high one cycle after Clk_out1 when Rst is de-asserted. The outputs are out of phase. Inspect the circuit and correct the fault.
Constraints
- Do not add additional flip-flops to the design.
- Both outputs must maintain a 50 percent duty cycle at exactly one quarter of the master clock frequency.
Topics
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