Clock Enable Generator

Modern digital designs avoid creating multiple derived clock domains. Using flip-flops to divide a high-speed clock complicates timing analysis, synthesis, and clock tree routing. The industry standard approach relies on a single high-speed clock while generating a one-cycle enable pulse to pace downstream logic. This keeps all sequential elements in the same clock domain while achieving the functional equivalent of a slower clock.

The module generates a single-cycle pulse on pulse_out every divide_by clock cycles, provided enable_in is asserted. It maintains an internal counter that increments when enable_in is high. When the counter reaches divide_by - 1, pulse_out is asserted high combinationally. On the next clock cycle, assuming enable_in remains high, the counter wraps back to zero and pulse_out returns low. If enable_in is de-asserted, the counter holds its current value and pulse_out is immediately driven low.

Clock edge is posedge clk. Reset is asynchronous and active-low via rst_n. On reset, the internal counter resets to 0 and pulse_out outputs 0. Reset has the highest priority. De-asserting enable_in immediately forces pulse_out to 0, overriding any pulse that would have occurred, and prevents the counter from incrementing.

Trace for divide_by = 3: Cycle 1: rst_n=0, enable_in=0 → count=0, pulse_out=0 Cycle 2: rst_n=1, enable_in=1 → count=1, pulse_out=0 Cycle 3: enable_in=1 → count=2, pulse_out=1 Cycle 4: enable_in=1 → count=0, pulse_out=0 Cycle 5: enable_in=1 → count=1, pulse_out=0 Cycle 6: enable_in=0 → count=1 (hold), pulse_out=0 Cycle 7: enable_in=1 → count=2, pulse_out=1 Cycle 8: enable_in=1 → count=0, pulse_out=0

{
  "signal": [
    { "name": "clk",       "wave": "p........" },
    { "name": "rst_n",     "wave": "01......." },
    { "name": "enable_in", "wave": "01...01.." },
    { "name": "divide_by", "wave": "3........" },
    {},
    { "name": "count",     "wave": "=.=.=.=.=.=.=.=.=.", "data": ["0", "1", "2", "0", "1", "1", "2", "0", "1"] },
    { "name": "pulse_out", "wave": "0.10..10." }
  ],
  "head": { "text": "Clock enable generation with divide_by = 3." }
}

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; counter and output go to 0 | | enable_in | input | 1 | Master enable; counter increments and pulse can be generated when 1 | | divide_by | input | 8 | Division factor N; valid range is 2 to 255 | | pulse_out | output | 1 | High for one cycle when counter reaches N-1 and enable is 1 |

Constraints

• Clock edge is posedge clk.
• Reset is asynchronous and active-low.
• Output pulse_out must be 0 when rst_n is 0.
• De-asserting enable_in has priority over pulse generation; if enable_in is 0, pulse_out must be 0 immediately.
• The internal counter must wrap to 0 the cycle after reaching divide_by - 1.
• The divide_by input is guaranteed to be between 2 and 255; you do not need to handle 0 or 1.
• pulse_out must be evaluated combinationally based on the registered counter and enable_in.

Topics

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