The Glitchy Clock Multiplexer

Modern System-on-Chips frequently transition between power states, requiring clock domains to switch dynamically between a fast, power-hungry PLL clock and a slow, low-power oscillator. A naive combinational multiplexer will generate runt pulses or glitches during the transition, violating setup and hold times and corrupting downstream state across the entire chip.

The solution module must safely switch the output clock between two free-running asynchronous clocks based on a select signal. When the select signal changes, the module must ensure a clean, break-before-make handoff. The current clock's enable must be fully de-asserted and synchronized into the new clock's domain before the new clock's enable can be asserted. This prevents any overlapping high periods that would cause a glitch.

To achieve this, you must implement a classic two-stage synchronizer feedback loop. Each clock domain requires its own two-stage synchronizer to process the enable signals. To prevent the enable signal from changing while the clock is high, all synchronization flip-flops must be triggered on the negative edge of their respective clocks.

Port Table

| Signal | Direction | Width | Description | | :--- | :--- | :--- | :--- | | clk_a | input | 1 | First asynchronous free-running clock | | clk_b | input | 1 | Second asynchronous free-running clock | | rst_n | input | 1 | Asynchronous active-low reset; drives output to 0 and clears all internal registers | | sel | input | 1 | Clock select signal; 0 selects clk_a, 1 selects clk_b | | clk_out | output | 1 | The multiplexed clock output |

Worked Trace

• Event 1: rst_n=0, sel=0, clk_a=0, clk_b=0 → clk_out=0
• Event 2: rst_n=1, clk_a negedge 1 → A-domain sync stage 1 loaded
• Event 3: clk_a negedge 2 → A-domain sync stage 2 loaded, domain A enabled
• Event 4: clk_a goes high → clk_out=1 (following clk_a)
• Event 5: sel=1 → select changes to B, but domain A remains enabled
• Event 6: clk_a negedge 1 → A-domain sync stage 1 cleared
• Event 7: clk_a negedge 2 → A-domain sync stage 2 cleared, domain A disabled
• Event 8: clk_b negedge 1 → B-domain sync stage 1 loaded (since domain A is now disabled)
• Event 9: clk_b negedge 2 → B-domain sync stage 2 loaded, domain B enabled
• Event 10: clk_b goes high → clk_out=1 (following clk_b)

Constraints

• All synchronization flip-flops must be negative-edge triggered.
• You must use exactly two flip-flops in sequence for each clock domain's synchronizer.
• The design must not produce any pulses shorter than the high-time of either clock.
• rst_n must asynchronously clear all internal registers to 0.
• The final output must be a combinational logic function of the clocks and the synchronized enable signals.

Topics

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