Glitch Free Clock Multiplexer

Modern system-on-chip designs rely on dynamic voltage and frequency scaling to balance performance and power. A core component of this architecture is the clock multiplexer, which switches the active clock source on the fly without introducing glitches or runt pulses that would violate setup and hold times in downstream logic.

The module takes two independent, asynchronous clocks (clk_a and clk_b) and routes one of them to clk_out based on the sel signal. When sel transitions, the currently active clock must be cleanly gated off. The system must wait until the active clock is confirmed disabled before enabling the new clock. This break-before-make behavior prevents overlapping clock pulses. To prevent cutting off a clock pulse mid-cycle, the gating signals must only transition when their respective clocks are low.

Timing and Reset Rules

• Clock edges: All internal synchronization and gating flip-flops must be clocked on the negative edge (negedge) of their respective clocks (clk_a or clk_b).
• Reset: rst_n is an asynchronous, active-low reset. When asserted, all internal flip-flops must be cleared to 0, driving clk_out to 0.
• Priority and Feedback: The enable signal for domain A is driven by ~sel ANDed with the inverted final gating signal of domain B. The enable signal for domain B is driven by sel ANDed with the inverted final gating signal of domain A.
• Synchronization: Each clock domain requires a 2-stage negative-edge synchronizer for its enable signal.
• Output: clk_out is strictly combinational, combining the clocks and their synchronized enable signals.

Worked Trace

• Cycle 1: rst_n=0. All synchronizers reset to 0. clk_out=0.
• Cycle 2: rst_n=1, sel=0. Domain A enable becomes 1.
• Cycle 3: clk_a negedge. Domain A stage 1 synchronizer becomes 1.
• Cycle 4: clk_a negedge. Domain A stage 2 synchronizer becomes 1. clk_out now follows clk_a.
• Cycle 5: sel=1. Domain A enable becomes 0.
• Cycle 6: clk_a negedge. Domain A stage 1 synchronizer becomes 0.
• Cycle 7: clk_a negedge. Domain A stage 2 synchronizer becomes 0. clk_a is gated off. Domain B enable becomes 1.
• Cycle 8: clk_b negedge. Domain B stage 1 synchronizer becomes 1.
• Cycle 9: clk_b negedge. Domain B stage 2 synchronizer becomes 1. clk_out follows clk_b.

Diagram

{ "signal": [
  { "name": "clk_a",   "wave": "1010101010101010" },
  { "name": "clk_b",   "wave": "0101010101010101" },
  { "name": "sel",     "wave": "0...1..........." },
  { "name": "sync_a2", "wave": "1.....0........." },
  { "name": "sync_b2", "wave": "0.......1......." },
  { "name": "clk_out", "wave": "1010100001010101" }
], "head": { "text": "Break-before-make clock switching." } }

Port Table

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk_a | input | 1 | First clock source | | clk_b | input | 1 | Second clock source | | rst_n | input | 1 | Asynchronous active-low reset; clears all synchronizers | | sel | input | 1 | Clock select; 0 outputs clk_a, 1 outputs clk_b | | clk_out| output | 1 | Glitch-free multiplexed clock output |

Constraints

• All flip-flops must be triggered on the negative edge of their respective clocks.
• The output clk_out must be strictly combinational logic.
• A 2-stage synchronizer must be used in both clock domains.
• Asynchronous active-low reset must clear all internal flip-flops to 0.

Topics

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