Simple Latch Based Clock Gating Cell

Modern SoCs rely heavily on clock gating to reduce dynamic power consumption. Naively gating a clock with a simple AND gate introduces hazardous glitches if the enable signal transitions while the clock is high.

A standard glitch-free clock gating cell solves this by synchronizing the enable signal. The circuit uses a negative-level sensitive latch to hold the enable signal steady during the high phase of the clock. The latched enable is then ANDed with the source clock to produce the gated clock. This ensures the output clock transitions cleanly and safely.

Timing and Reset Rules:

• Latch transparency: The internal latch is transparent when clk is 0; it directly passes the en signal.
• Latch hold: The internal latch holds its current value when clk is 1, ignoring any changes on en.
• Output logic: The gated_clk output is a combinational AND of clk and the internal latched enable.
• Reset: There is no explicit reset pin; the latch assumes the value of en when clk is 0.

Worked Trace:

Step 1: clk=0, en=1 → latched_en=1, gated_clk=0 Step 2: clk=1, en=1 → latched_en=1 (hold), gated_clk=1 Step 3: clk=1, en=0 → latched_en=1 (hold), gated_clk=1 (glitch prevented) Step 4: clk=0, en=0 → latched_en=0, gated_clk=0 Step 5: clk=0, en=1 → latched_en=1, gated_clk=0 Step 6: clk=1, en=1 → latched_en=1 (hold), gated_clk=1

{ "signal": [
  { "name": "clk",       "wave": "01.0.1" },
  { "name": "en",        "wave": "1.0..1" },
  {},
  { "name": "latched_en","wave": "1..0.1" },
  { "name": "gated_clk", "wave": "01.0.1" }
], "head": { "text": "Enable falls while clk is high; latch holds value to prevent output glitch." } }

Port Table:

| Signal | Direction | Width | Description | |-------------|-----------|-------|-------------| | clk | input | 1 | Source clock | | en | input | 1 | Clock enable signal | | gated_clk | output | 1 | Gated output clock |

Constraints

• Must infer a negative-level sensitive latch for the internal enable signal.
• Do not use edge-triggered flip-flops (posedge or negedge).
• The output gated_clk must be the continuous logical AND of clk and the latched enable.
• All ports are 1-bit wide.

Topics

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