Divide by N Even with Fifty Percent Duty Cycle
System-on-Chip (SoC) designs often require multiple clock frequencies derived from a single high-speed phase-locked loop (PLL) reference clock. A parameterized clock divider allows engineers to instantiate flexible frequency generators across the chip without rewriting custom counter logic for every required ratio.
The module divides the frequency of the input clock by an even integer parameter N to produce an output clock with a 50% duty cycle. The output clock transitions every N/2 input clock cycles.
Timing and reset rules: • Clock edge: posedge clk • Reset type: Asynchronous • Reset polarity: Active-low (rst_n) • Reset behavior: On reset, clk_out is driven to 0 and all internal counters are cleared to 0 immediately. • Operation: The internal counter increments on every positive edge of clk. When the counter reaches (N/2) - 1, the output clk_out toggles, and the counter resets to 0.
Worked trace for N=4:
Cycle 1: rst_n=0 → clk_out=0, count=0
Cycle 2: rst_n=1 → clk_out=0, count=1
Cycle 3: rst_n=1 → clk_out=1, count=0 (toggled)
Cycle 4: rst_n=1 → clk_out=1, count=1
Cycle 5: rst_n=1 → clk_out=0, count=0 (toggled)
Cycle 6: rst_n=1 → clk_out=0, count=1{ "signal": [
{ "name": "clk", "wave": "p........." },
{ "name": "rst_n", "wave": "01........" },
{ "name": "count", "wave": "==========", "data": ["0", "1", "0", "1", "0", "1", "0", "1", "0", "1"] },
{ "name": "clk_out", "wave": "0.1.0.1.0." }
], "head": { "text": "Divide by 4 operation showing 50% duty cycle." } }| Parameter | Default | Description | |-----------|---------|-------------| | N | 4 | Even integer division ratio |
| Signal | Direction | Width | Description | |-----------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; clk_out goes to 0 when asserted | | clk_out | output | 1 | Divided clock output with 50% duty cycle |
Constraints
Nis guaranteed to be an even integer greater than or equal to 2.- Clock edge is
posedge clk. - Reset is asynchronous and active-low.
- On reset,
clk_outand any internal counters must immediately go to 0. clk_outmust be a registered output.
Topics
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