Clocked D Latch (Level-Triggered) from NAND Gates
The clocked D latch is the level-triggered precursor to the edge-triggered D flip-flop. It is transparent: when the clock (enable) is high, the output Q follows D continuously. When the clock is low, Q holds its last value. Timing-aware engineers must know the latch's transparent window — a signal change during the high phase immediately propagates to the output, unlike a flip-flop which only samples at the clock edge. Latch-based designs appear in high-performance CPUs where the transparency is deliberately exploited to borrow time across pipeline stages.
Your task is to implement a clocked D latch using exactly 4 NAND2 gates. The circuit is built by wrapping a NAND SR-latch (2 NAND gates) with two steering gates that connect the data input D and the enable input EN. When EN=1, the latch is transparent: Q follows D. When EN=0, Q holds its value.
The circuit structure: Gate 1 computes NAND(EN, D), producing the S̄ signal. Gate 2 computes NAND(EN, NOT_D), where NOT_D = NAND(D, D), producing the R̄ signal. Gates 3 and 4 form the cross-coupled SR-latch: Q = NAND(S̄, Qbar) and Qbar = NAND(R̄, Q). The NOT_D signal is generated by Gate 0 = NAND(D, D), making the total 4 NAND gates.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | D | input | 1 | Data input: the value to capture when EN=1 | | EN | input | 1 | Enable (clock): when 1, Q transparently follows D; when 0, Q holds | | Q | output | 1 | Latch output |
Constraints
- Only NAND2 gates are allowed. Exactly 4 NAND2 gates are required for the optimal solution.
- When EN=1 and D changes, Q changes immediately (within propagation delay) — there is no clock edge synchronization.
- When EN=0, Q holds regardless of what D does. The holding behavior comes from the cross-coupled SR core.
- S=1, R=1 cannot occur simultaneously when built correctly — the steering logic prevents it because S̄ = NAND(EN,D) and R̄ = NAND(EN,NOT_D) cannot both be 0 at the same time (since D and NOT_D cannot both be 1).
Topics
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