Continuous Counter Debounce

Mechanical switches bounce, causing rapid, unpredictable toggling when pressed or released. Digital systems must filter these spurious transitions to prevent state machines from triggering multiple times for a single physical event.

A continuous counter debounce circuit monitors an asynchronous input signal. It requires the input to remain at a new, stable logic level for a consecutive number of clock cycles before updating the output. If the input glitches or reverts to its previous state before the threshold is reached, the internal counter completely resets. The output only transitions once the input has held the new state for the full duration.

The module operates on a positive clock edge posedge clk and uses an asynchronous, active-low reset rst_n. On reset, both the internal counter and the debounced output clean_out must be forced to 0. A parameter THRESHOLD defines the number of consecutive stable clock cycles required to register a change. When noisy_in differs from clean_out, the counter increments. If noisy_in matches clean_out, the counter synchronously resets to 0. When the counter reaches THRESHOLD, clean_out updates to match noisy_in and the counter resets to 0.

Cycle 1: rst_n=0 → clean_out=0, count=0 Cycle 2: rst_n=1, noisy_in=1 → clean_out=0, count=1 Cycle 3: rst_n=1, noisy_in=0 → clean_out=0, count=0 Cycle 4: rst_n=1, noisy_in=1 → clean_out=0, count=1 Cycle 5: rst_n=1, noisy_in=1 → clean_out=0, count=2 Cycle 6: rst_n=1, noisy_in=1 → clean_out=0, count=3 Cycle 7: rst_n=1, noisy_in=1 → clean_out=1, count=0 Cycle 8: rst_n=1, noisy_in=1 → clean_out=1, count=0

{ "signal": [
  { "name": "clk",       "wave": "p......." },
  { "name": "rst_n",     "wave": "01......" },
  { "name": "noisy_in",  "wave": "0101...." },
  { "name": "clean_out", "wave": "0......1" },
  { "name": "count",     "wave": "========", "data": ["0","1","0","1","2","3","0","0"] }
], "head": { "text": "Counter resets on glitch, then completes full cycle to update output." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; sets clean_out and internal counter to 0 | | noisy_in | input | 1 | The raw bouncing input signal | | clean_out | output | 1 | The debounced output signal; resets to 0 |

Constraints

• Output clean_out and the internal counter must asynchronously reset to 0 when rst_n is 0
• The counter must increment on posedge clk only when noisy_in differs from clean_out
• If noisy_in equals clean_out, the counter must synchronously reset to 0
• When the counter reaches THRESHOLD, clean_out must update to noisy_in on the same clock edge, and the counter must reset to 0
• The module must include a parameter THRESHOLD with a default value of 4

Topics

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