Count Leading Sign Bits
Digital signal processors and floating point units frequently normalize signed numbers to maximize dynamic range before performing arithmetic. Normalization requires shifting the value left to remove redundant sign bits. To determine the exact shift amount, the hardware needs a circuit that counts how many of these redundant bits exist before the first significant bit.
The solution module evaluates a 16 bit signed integer and counts the number of consecutive bits immediately following the most significant bit (MSB) that match the MSB. The count starts at bit 14 and proceeds downwards to bit 0. The search stops at the first bit that differs from the MSB. If all bits in the word match the MSB, the output reflects the maximum possible redundant bits.
This is a purely combinational circuit. There is no clock or reset. The output must update immediately and continuously based on the current input value.
| Signal | Direction | Width | Description | |---------|-----------|-------|-------------| | in | input | 16 | Signed input value | | count | output | 4 | Purely combinational output representing the number of leading sign bits (0 to 15) |
Constraints
- The module must be purely combinational.
- The
countoutput must be exactly 4 bits wide to represent values from 0 to 15. - The MSB (
in[15]) is the reference sign bit and is not included in the count itself; the maximum count of matching bits is 15.
Topics
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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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