Data Multiplexer Synchronization

Passing wide configuration buses across clock domains using FIFOs consumes significant area and power. When a bus updates rarely and throughput is not a concern, multiplexer recirculation provides a highly efficient alternative. The control signal is synchronized to the destination domain, where it acts as a select line for a multiplexer that either loads the new bus value or recirculates the existing value indefinitely.

The module receives a 32-bit tx_data bus and a tx_valid pulse in the source clock domain. The tx_valid pulse toggles a control register, converting the single-cycle pulse into a level change. This toggle signal is passed through a two-stage synchronizer into the destination clock domain. In the destination domain, a third flip-flop acts as a delay element to detect edges (both rising and falling) on the synchronized toggle signal. A 32-bit destination register uses a multiplexer to hold its current value until the edge detector outputs a pulse, at which point it samples the tx_data bus.

• Clocks: clk_tx and clk_rx are positive-edge triggered.
• Resets: rst_tx_n and rst_rx_n are asynchronous and active-low.
• When rst_tx_n is asserted, the source toggle register resets to 0.
• When rst_rx_n is asserted, all destination synchronizer flip-flops and the rx_data register reset to 0.
• The tx_data bus is held stable by external logic long enough to safely pass the synchronization window.

Cycle 1 (TX): rst_tx_n=0, rst_rx_n=0 → tx_toggle=0, rx_data=0 Cycle 2 (TX): rst_tx_n=1, tx_valid=1, tx_data=42 → tx_toggle toggles to 1 Cycle 3 (RX): rst_rx_n=1 → sync1=1, sync2=0, sync3=0, edge_pulse=0, rx_data=0 Cycle 4 (RX): sync1=1, sync2=1, sync3=0 → edge_pulse=1, rx_data=0 Cycle 5 (RX): sync1=1, sync2=1, sync3=1 → edge_pulse=0, rx_data=42 (sampled from tx_data) Cycle 6 (RX): sync1=1, sync2=1, sync3=1 → edge_pulse=0, rx_data=42 (recirculated)

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk_tx | input | 1 | Positive-edge triggered clock for the source domain | | rst_tx_n | input | 1 | Asynchronous active-low reset for the source domain | | clk_rx | input | 1 | Positive-edge triggered clock for the destination domain | | rst_rx_n | input | 1 | Asynchronous active-low reset for the destination domain | | tx_data | input | 32 | Source data bus; held stable by external logic | | tx_valid | input | 1 | Source valid pulse; asserts for one clk_tx cycle to initiate a transfer | | rx_data | output | 32 | Destination data bus; updates when the synchronized pulse is detected |

Constraints

• Use a toggle register in the TX domain that flips state every time tx_valid is 1.
• Use a 2-flip-flop synchronizer in the RX domain to safely capture the toggle signal.
• Use a third flip-flop in the RX domain to detect edges (both rising and falling) on the synchronized toggle signal.
• The rx_data output must be a registered output that recirculates its value unless an edge is detected.
• The tx_data bus must not be passed through synchronizer flip-flops; it is sampled directly by rx_data.

Topics

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