Multi Clock Domain Reset Sequencer

HardVerilog / SystemVerilogBuild

Complex Systems on Chip require strict boot sequencing to prevent bus lockups during reset. A master controller manages system bring-up across multiple domains, ensuring each subsystem is fully operational before the next is activated. When releasing resets across clock boundaries, the sequencer must wait for the target domain to acknowledge its active state before proceeding to the next domain.

The solution module acts as a master reset sequencer for four distinct clock domains. Upon receiving a master enable signal, it sequentially deasserts the reset to domain 0, waits for an acknowledgment from domain 0, then proceeds to domain 1, continuing up to domain 3. If the master reset is asserted at any point, all domain resets must immediately assert asynchronously. If the master enable drops during the sequence, the controller must pause its progression and hold its current state until the enable is restored.

Timing and Reset Rules

Clock edge: posedge clk
Reset type: Asynchronous active-low via rst_n
Output values on reset: dom_rst_n = 4'b0000, seq_done = 1'b0
Priority rules: rst_n overrides all other inputs and internal state immediately.
The bring-up sequence begins when master_en is 1.
Domain i reset is released (set to 1) sequentially. The sequencer waits for dom_ack[i] to be 1 before releasing dom_rst_n[i+1] on the next clock cycle.
If master_en goes to 0 during the sequence, the sequencer pauses its progression but holds current outputs.
seq_done becomes 1 on the cycle after dom_ack[3] is received, provided master_en is 1.
All outputs must be registered.

Worked Trace

Cycle 1: rst_n=0 → dom_rst_n=4'b0000, seq_done=0 Cycle 2: rst_n=1, master_en=1, dom_ack=4'b0000 → dom_rst_n=4'b0001, seq_done=0 (releasing domain 0) Cycle 3: rst_n=1, master_en=1, dom_ack=4'b0000 → dom_rst_n=4'b0001, seq_done=0 (waiting for domain 0 ack) Cycle 4: rst_n=1, master_en=1, dom_ack=4'b0001 → dom_rst_n=4'b0011, seq_done=0 (ack 0 received, releasing domain 1) Cycle 5: rst_n=1, master_en=0, dom_ack=4'b0011 → dom_rst_n=4'b0011, seq_done=0 (master_en dropped, pausing) Cycle 6: rst_n=1, master_en=1, dom_ack=4'b0011 → dom_rst_n=4'b0111, seq_done=0 (master_en restored, ack 1 received, releasing domain 2) Cycle 7: rst_n=1, master_en=1, dom_ack=4'b0111 → dom_rst_n=4'b1111, seq_done=0 (ack 2 received, releasing domain 3) Cycle 8: rst_n=1, master_en=1, dom_ack=4'b0111 → dom_rst_n=4'b1111, seq_done=0 (waiting for domain 3 ack) Cycle 9: rst_n=1, master_en=1, dom_ack=4'b1111 → dom_rst_n=4'b1111, seq_done=1 (ack 3 received, sequence complete) Cycle 10: rst_n=1, master_en=1, dom_ack=4'b1111 → dom_rst_n=4'b1111, seq_done=1 (hold state)

Diagram

{ "signal": [
  { "name": "clk", "wave": "p........." },
  { "name": "rst_n", "wave": "01........" },
  { "name": "master_en", "wave": "01..01...." },
  { "name": "dom_ack", "wave": "==========", "data": ["0","0","0","1","3","3","7","7","15","15"] },
  { "name": "dom_rst_n", "wave": "==========", "data": ["0","1","1","3","3","7","15","15","15","15"] },
  { "name": "seq_done", "wave": "0.......1." }
], "head": { "text": "Sequence with a pause and varying acknowledgment delays." } }

Port Table

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; all outputs go to 0 when asserted | | master_en | input | 1 | Master enable; sequence advances when 1, pauses when 0 | | dom_ack | input | 4 | Acknowledgment from each clock domain (1 bit per domain) | | dom_rst_n | output | 4 | Registered reset release to each domain (active-low reset, so 1 means released) | | seq_done | output | 1 | Registered flag indicating all domains are active |

Constraints

Clock edge must be strictly posedge clk.
Reset must be strictly asynchronous and active-low.
All outputs must be registered; no combinational paths from inputs directly to outputs.
If dom_ack[i] drops unexpectedly after being asserted, the state machine must NOT revert (it only advances forward or resets entirely via rst_n).
The sequence strictly waits for dom_ack[i] to be 1 before driving dom_rst_n[i+1] to 1.

Topics

Clock Domain CrossingState MachineSystem Bring-up

Solve this problem

Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.

This problem is part of Codiode Pro. The statement above is free to read.

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

Constraints

Clock edge must be strictly posedge clk.
Reset must be strictly asynchronous and active-low.
All outputs must be registered; no combinational paths from inputs directly to outputs.
If dom_ack[i] drops unexpectedly after being asserted, the state machine must NOT revert (it only advances forward or resets entirely via rst_n).
The sequence strictly waits for dom_ack[i] to be 1 before driving dom_rst_n[i+1] to 1.

Topics

Clock Domain CrossingState MachineSystem Bring-up

Solve this problem

Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.

This problem is part of Codiode Pro. The statement above is free to read.

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

Multi Clock Domain Reset Sequencer

Timing and Reset Rules

Worked Trace

Diagram

Port Table

Constraints

Topics

Solve this problem

Related problems

Multi Clock Domain Reset Sequencer

Timing and Reset Rules

Worked Trace

Diagram

Port Table

Constraints

Topics

Solve this problem

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