Derived Clock Used as Data Signal
A system control block generates a divided clock for a low-speed peripheral and feeds the peripheral's clock state back into the main high-speed domain.
Expected behavior:
| Reset | Clk | DivClk | DataOut | |---------|-------|----------|-----------| | 1 | 0 | 0 | 0 | | 0 | 1 | 1 | 0 | | 0 | 0 | 1 | 0 | | 0 | 1 | 0 | 1 | | 0 | 0 | 0 | 1 | | 0 | 1 | 1 | 0 |
Simulation shows DataOut = X (metastable) immediately following the first rising edge of Clk after Reset is deasserted. The test bench reports a hold time violation on the capture register because its data input transitions at the exact same time as its active clock edge. Inspect the circuit and correct the fault.
Constraints
- Do not change the frequency or phase of
DivClk. DataOutmust reliably capture the state ofDivClkusing the mainClkdomain.- Use standard synchronization techniques to resolve the timing violation.
Topics
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