Divide by Two Using Logic Gate
A clock divider reduces the frequency of an input signal by toggling its output on every rising edge of the source clock.
Expected behavior:
| Time | Reset | ClkIn | ClkOut | |------|---------|---------|----------| | 0 | 1 | 0 | 0 | | 1 | 0 | 1 | 1 | | 2 | 0 | 0 | 1 | | 3 | 0 | 1 | 0 | | 4 | 0 | 0 | 0 |
Simulation shows ClkOut = 0 at Time 2 when ClkIn = 0. The output fails to hold its state during the negative phase of the input clock. Inspect the circuit and correct the fault.
Constraints
- The output
ClkOutmust be driven directly by a register to ensure a glitch-free clock domain. - Do not use combinational logic to gate or derive the output clock signal.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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