Double Stage Forwarding with Priority

HardVerilog / SystemVerilogBuild

Pipelined processors overlap instruction execution, which introduces data hazards when a dependent instruction needs a result that has not yet been written back to the register file. Forwarding paths solve this by bypassing the register file and providing the necessary data directly from later pipeline stages. In a classic 5-stage pipeline, both the memory stage (EX/MEM) and the writeback stage (MEM/WB) can potentially forward data back to the operand fetch stage.

The forwarding unit compares the source register addresses (rs1_addr, rs2_addr) of the current instruction against the destination register addresses (ex_mem_rd, mem_wb_rd) of the instructions currently in the EX/MEM and MEM/WB stages. If a match is found and the corresponding stage is actively writing to the register file (regwrite is 1), the unit forwards the data from that stage instead of using the stale default register data (rs1_data, rs2_data). If both stages write to the same source register, the EX/MEM stage holds the most recent data and must take strict priority. The resolved operands are then latched into output registers for the next pipeline stage.

The module is driven by a positive-edge triggered clock clk and an asynchronous active-low reset rst_n. On reset, both output registers out_op1 and out_op2 must be driven to 0.

Cycle by cycle execution trace: • Cycle 1: rst_n=0. Outputs out_op1 and out_op2 are forced to 0. • Cycle 2: rst_n=1. Inputs are rs1_addr=1, rs1_data=10. No forwarding matches occur. On the clock edge, out_op1 updates to 10. • Cycle 3: rs1_addr=3, ex_mem_rd=3, ex_mem_regwrite=1, ex_mem_data=30. On the clock edge, out_op1 updates to 30. • Cycle 4: rs1_addr=5. Both ex_mem_rd=5 (ex_mem_data=50) and mem_wb_rd=5 (mem_wb_data=60) match with active regwrite. EX/MEM takes priority. On the clock edge, out_op1 updates to 50. • Cycle 5: rs1_addr=0, ex_mem_rd=0, ex_mem_regwrite=1 (ex_mem_data=99). Register 0 cannot be forwarded to. On the clock edge, out_op1 updates to 0 (using rs1_data).

{ "signal": [
  { "name": "clk", "wave": "p...." },
  { "name": "rst_n", "wave": "01..." },
  { "name": "rs1_addr", "wave": "x====", "data": ["1", "3", "5", "0"] },
  { "name": "ex_mem_rd", "wave": "x====", "data": ["3", "3", "5", "0"] },
  { "name": "mem_wb_rd", "wave": "x====", "data": ["4", "4", "5", "0"] },
  { "name": "out_op1", "wave": "=.===", "data": ["0", "10", "30", "50", "0"] }
], "head": { "text": "Cycle-by-cycle forwarding resolution." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; outputs go to 0 when asserted | | rs1_addr | input | 5 | Source register 1 address | | rs2_addr | input | 5 | Source register 2 address | | rs1_data | input | 32 | Default data for source register 1 from the register file | | rs2_data | input | 32 | Default data for source register 2 from the register file | | ex_mem_rd | input | 5 | Destination register address in EX/MEM stage | | ex_mem_data | input | 32 | Data to be written by EX/MEM stage | | ex_mem_regwrite | input | 1 | Write enable from EX/MEM stage | | mem_wb_rd | input | 5 | Destination register address in MEM/WB stage | | mem_wb_data | input | 32 | Data to be written by MEM/WB stage | | mem_wb_regwrite | input | 1 | Write enable from MEM/WB stage | | out_op1 | output | 32 | Registered operand 1; resets to 0 | | out_op2 | output | 32 | Registered operand 2; resets to 0 |

Constraints

The module must trigger on the positive edge of clk and reset asynchronously on the active-low rst_n.
The outputs out_op1 and out_op2 must be registered and default to 0 on reset.
Register 0 (5'b00000) is hardwired to zero in RISC architectures. If a source address is 0, the forwarding logic must ignore any matches and output the corresponding rs_data.
Priority rule: If both EX/MEM and MEM/WB stages have a valid forwarding match for the same register, the EX/MEM stage takes strict priority.
A forwarding match only occurs if the stage's regwrite signal is asserted.

Topics

PipeliningForwardingData HazardsRegister Fetch

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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.

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Constraints

The module must trigger on the positive edge of clk and reset asynchronously on the active-low rst_n.
The outputs out_op1 and out_op2 must be registered and default to 0 on reset.
Register 0 (5'b00000) is hardwired to zero in RISC architectures. If a source address is 0, the forwarding logic must ignore any matches and output the corresponding rs_data.
Priority rule: If both EX/MEM and MEM/WB stages have a valid forwarding match for the same register, the EX/MEM stage takes strict priority.
A forwarding match only occurs if the stage's regwrite signal is asserted.

Topics

PipeliningForwardingData HazardsRegister Fetch

Solve this problem

Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.

This problem is part of Codiode Pro. The statement above is free to read.

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

Double Stage Forwarding with Priority

Constraints

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Double Stage Forwarding with Priority

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