Load Use Hazard Detection

MediumVerilog / SystemVerilogBuild

Pipelined processors rely on data forwarding to resolve most read-after-write hazards without stalling. However, when an instruction loads a value from memory, the data does not become available until the end of the Memory stage. If the immediately following instruction requires this data for its Execute stage, forwarding alone cannot resolve the dependency. The pipeline must stall for one cycle to allow the memory read to complete.

The hazard detection unit monitors the pipeline registers to identify this specific condition. It compares the destination register of the instruction currently in the Execute stage against the source registers of the instruction in the Instruction Decode stage. If the Execute stage instruction is a memory load, its destination register is not register zero, and it matches either of the Decode stage source registers, a load-use hazard is detected and a stall is issued.

Clock edge: posedge clk
Reset type: Asynchronous active-low rst_n
Reset polarity: All outputs go to 0 when rst_n is 0
Priority: Reset has the highest priority. Matches on register 0 are always ignored.
The stall output is registered and updates on the positive edge of clk.

Cycle 1: rst_n=0 → stall=0
Cycle 2: rst_n=1, id_ex_mem_read=1, id_ex_rd=1, if_id_rs1=2, if_id_rs2=3 → stall=0 (no hazard detected)
Cycle 3: id_ex_mem_read=1, id_ex_rd=5, if_id_rs1=5, if_id_rs2=2 → stall=0 (hazard on rs1 detected; output updates on next edge)
Cycle 4: id_ex_mem_read=0, id_ex_rd=0, if_id_rs1=0, if_id_rs2=0 → stall=1 (pipeline is stalled)
Cycle 5: id_ex_mem_read=1, id_ex_rd=0, if_id_rs1=0, if_id_rs2=0 → stall=0 (hazard resolved; match on register 0 is ignored)
Cycle 6: id_ex_mem_read=1, id_ex_rd=9, if_id_rs1=2, if_id_rs2=9 → stall=0 (hazard on rs2 detected)
Cycle 7: id_ex_mem_read=0, id_ex_rd=0, if_id_rs1=0, if_id_rs2=0 → stall=1 (pipeline is stalled)
Cycle 8: id_ex_mem_read=0, id_ex_rd=0, if_id_rs1=0, if_id_rs2=0 → stall=0 (hazard resolved)

{ "signal": [
  { "name": "clk", "wave": "p......." },
  { "name": "rst_n", "wave": "01......" },
  { "name": "id_ex_mem_read", "wave": "01101100" },
  { "name": "id_ex_rd", "wave": "0=======", "data": ["1","5","0","0","9","0","0"] },
  { "name": "if_id_rs1", "wave": "0=======", "data": ["2","5","0","0","2","0","0"] },
  { "name": "if_id_rs2", "wave": "0=======", "data": ["3","2","0","0","9","0","0"] },
  {},
  { "name": "stall", "wave": "0..10.10" }
], "head": { "text": "Load-use hazard detection trace over 8 cycles." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; stall goes to 0 when asserted | | id_ex_mem_read | input | 1 | Asserts to 1 if the instruction in the EX stage is a memory load | | id_ex_rd | input | 5 | Destination register address of the instruction in the EX stage | | if_id_rs1 | input | 5 | First source register address of the instruction in the ID stage | | if_id_rs2 | input | 5 | Second source register address of the instruction in the ID stage | | stall | output | 1 | Registered output; asserts to 1 if a hazard is detected |

Constraints

The stall output must be registered and updated on the positive edge of clk.
Register 0 (5'b00000) is hardwired to zero in this architecture and never causes a data hazard. A match on register 0 must not trigger a stall.
Reset is asynchronous and active-low.

Topics

RegistersPipeliningHazard Detection

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