Forwarding After a Load Use Stall

HardVerilog / SystemVerilogBuild

Deep pipelined processors overlap instruction execution to maximize throughput, but data hazards occur when an instruction depends on a previous result. While most hazards can be resolved by forwarding data directly from the Memory or Writeback stages to the Execute stage, a load-use hazard requires special handling. When a load instruction reads from memory, the data is not available until the end of the Memory stage. If the immediately following instruction needs this data, the pipeline must stall for one cycle, inject a bubble, and then forward the delayed memory output.

You are designing a unified Hazard Detection and Forwarding Unit. The module tracks instruction metadata (source/destination registers and control flags) as they flow through the Execute (EX), Memory (MEM), and Writeback (WB) stages. It continuously monitors the Decode (ID) stage inputs against the EX stage state to detect load-use hazards. When a hazard is detected, it asserts a stall signal. On the next clock cycle, it injects a bubble into the EX stage while allowing the load instruction to proceed to MEM. It also computes the forwarding multiplexer controls (fwd_a and fwd_b) for the instruction currently in the EX stage.

To test this behavior, your module must internally track the instruction metadata as it flows through the pipeline. You must implement registers for the Execute (EX), Memory (MEM), and Writeback (WB) stages.

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; all internal pipeline registers go to 0 | | id_rs1 | input | 5 | Source register 1 of the instruction currently in Decode | | id_rs2 | input | 5 | Source register 2 of the instruction currently in Decode | | id_rd | input | 5 | Destination register of the instruction currently in Decode | | id_mem_read | input | 1 | Asserted if the instruction in Decode reads from memory | | id_reg_write | input | 1 | Asserted if the instruction in Decode writes to a register | | stall | output | 1 | Asserted if a load-use hazard is detected between EX and ID stages | | fwd_a | output | 2 | Forwarding control for EX stage ALU input A (corresponding to rs1) | | fwd_b | output | 2 | Forwarding control for EX stage ALU input B (corresponding to rs2) |

Forwarding Control Values: • 2'b00: No forwarding (use register file value) • 2'b10: Forward from the MEM stage (instruction currently in MEM) • 2'b01: Forward from the WB stage (instruction currently in WB)

Constraints

Clock edge is posedge clk; reset is asynchronous active-low rst_n.
On reset, all internal pipeline registers (EX, MEM, WB) are cleared to 0.
stall, fwd_a, and fwd_b are purely combinational outputs evaluated continuously based on the current ID inputs and the current state of the internal EX, MEM, and WB registers.
On the positive edge of clk, if stall is 0, the ID inputs shift into the EX registers, EX shifts to MEM, and MEM shifts to WB.
On the positive edge of clk, if stall is 1, the EX registers must be cleared to 0 (injecting a bubble). The existing EX registers still shift to MEM, and MEM shifts to WB.
A load-use hazard occurs when the instruction in EX reads memory, and its destination register matches either id_rs1 or id_rs2.
Register 0 (x0) is hardwired to zero in RISC architectures. It must never trigger a stall and must never be forwarded.
Forwarding priority: The MEM stage has priority over the WB stage if both stages contain an instruction writing to the same destination register required by the EX stage.

Topics

HazardsState MachinePipeliningForwarding

Solve this problem

Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.

This problem is part of Codiode Pro. The statement above is free to read.

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

Constraints

Clock edge is posedge clk; reset is asynchronous active-low rst_n.
On reset, all internal pipeline registers (EX, MEM, WB) are cleared to 0.
stall, fwd_a, and fwd_b are purely combinational outputs evaluated continuously based on the current ID inputs and the current state of the internal EX, MEM, and WB registers.
On the positive edge of clk, if stall is 0, the ID inputs shift into the EX registers, EX shifts to MEM, and MEM shifts to WB.
On the positive edge of clk, if stall is 1, the EX registers must be cleared to 0 (injecting a bubble). The existing EX registers still shift to MEM, and MEM shifts to WB.
A load-use hazard occurs when the instruction in EX reads memory, and its destination register matches either id_rs1 or id_rs2.
Register 0 (x0) is hardwired to zero in RISC architectures. It must never trigger a stall and must never be forwarded.
Forwarding priority: The MEM stage has priority over the WB stage if both stages contain an instruction writing to the same destination register required by the EX stage.

Topics

HazardsState MachinePipeliningForwarding

Solve this problem

Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.

This problem is part of Codiode Pro. The statement above is free to read.

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

Forwarding After a Load Use Stall

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Forwarding After a Load Use Stall

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