Pipelining a Large Adder

High-performance processors and digital signal processors often operate at clock frequencies that are too fast for a single 64-bit adder to complete its combinational logic in one cycle. Breaking the arithmetic operation into smaller, registered stages ensures the logic delay fits comfortably within the clock period.

The pipeline_adder module computes the 64-bit addition of a and b by splitting the operation into four 16-bit pipelined stages. The pipeline accepts new inputs on every clock cycle and produces the sum and carry-out with a latency of exactly 4 clock cycles. To maintain data alignment, the partial sums and carry bits must be passed through registers at each stage so that the final 64-bit sum correctly represents the addition of a and b from the exact same input cycle.

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n| input | 1 | Asynchronous active-low reset; clears all outputs and internal registers | | a | input | 64 | First operand | | b | input | 64 | Second operand | | sum | output | 64 | Pipelined 64-bit sum result | | cout | output | 1 | Pipelined carry-out bit |

Timing and Reset Rules

• Clock edge: posedge clk
• Reset type: asynchronous, active-low (negedge rst_n)
• Output values on reset: sum and cout must be exactly 0. All internal pipeline registers must also be cleared to 0.

Worked Trace

Cycle 1: rst_n=0 → sum=0, cout=0 Cycle 2: rst_n=1, a=1, b=2 (Operation A) → sum=0, cout=0 Cycle 3: a=5, b=5 (Operation B) → sum=0, cout=0 Cycle 4: a=0, b=0 → sum=0, cout=0 Cycle 5: a=0, b=0 → sum=0, cout=0 Cycle 6: a=0, b=0 → sum=3, cout=0 (Result of Operation A) Cycle 7: a=0, b=0 → sum=10, cout=0 (Result of Operation B)

Pipeline Timing

{ "signal": [
  { "name": "clk",   "wave": "p........." },
  { "name": "rst_n", "wave": "01........" },
  { "name": "a",     "wave": "x.====x...", "data": ["1","5","0","0"] },
  { "name": "b",     "wave": "x.====x...", "data": ["2","5","0","0"] },
  {},
  { "name": "sum",   "wave": "=xxxxx==xx", "data": ["0","3","10"] },
  { "name": "cout",  "wave": "=xxxxx==xx", "data": ["0","0","0"] }
], "head": { "text": "Pipeline latency of 4 clock cycles for consecutive additions." } }

Constraints

• Trigger on the positive edge of clk and negative edge of rst_n.
• All outputs and internal registers must be completely cleared to 0 on reset.
• The pipeline must have exactly a 4-cycle latency from input to output.
• The module must accept new inputs on every clock cycle (throughput of 1 operation per cycle).
• Do not use a single 64-bit addition (e.g., sum = a + b). The addition must be broken into four distinct 16-bit additions.

Topics

Related problems

• Basic D Flip FlopEasy
• Debug: Missing Edge in Sensitivity ListMedium
• Read After Write Hazard DetectionEasy
• Parameterized Interface with ModportsHard
• Struct Array PipelineHard
• T Flip Flop from D Flip Flop TemplateEasy
• Recursive Generate Reduction TreeHard
• Four Stage Shift RegisterEasy