Edge Detector Delayed by Extra Cycle
An I2C start condition detector identifies a falling edge on the data line while the clock line remains high. The circuit must assert the start flag exactly one clock cycle after the falling edge occurs.
Expected behavior:
| Cycle | SDA | SCL | START | |-------|-------|-------|---------| | 1 | 1 | 1 | 0 | | 2 | 0 | 1 | 0 | | 3 | 0 | 1 | 1 | | 4 | 0 | 1 | 0 |
Simulation shows START = 1 occurring one cycle too late. When SDA transitions from 1 to 0 at cycle 2 with SCL held at 1, the START signal asserts at cycle 4 instead of cycle 3. Inspect the circuit and correct the fault.
Constraints
- Do not change the combinational logic for the detection condition.
- Maintain synchronous design practices with a single clock domain.
Topics
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