Fast to Slow Domain Pulse Synchronizer

HardVerilog / SystemVerilogBuild

Interfacing high-speed logic with a slower system bus often requires sending single-cycle events across clock boundaries. When a fast clock domain generates a pulse, that pulse is frequently shorter than the period of the destination clock. A standard two-flop synchronizer will completely miss this event if the fast pulse falls between the active edges of the slow clock.

This module reliably transfers a single-cycle pulse from a fast clock domain to a slow clock domain. It operates by converting the incoming fast pulse into a level change by toggling a register. This level signal is wide enough to be safely captured by the slow clock. A standard two-stage synchronizer brings the level signal into the slow domain, and an edge detector recreates the single-cycle pulse in the destination domain.

Both clk_fast and clk_slow are positive-edge triggered.
Both rst_fast_n and rst_slow_n are asynchronous, active-low resets.
When rst_fast_n is asserted, all fast-domain logic resets to 0.
When rst_slow_n is asserted, all slow-domain logic and pulse_out reset to 0.
pulse_in is exactly one clk_fast cycle wide.
pulse_out must be exactly one clk_slow cycle wide for every pulse_in received.
The module must safely handle consecutive pulses, provided they are separated by enough time for the slow domain to process the first toggle.

{ "signal": [
  { "name": "clk_fast",   "wave": "p..............." },
  { "name": "pulse_in",   "wave": "010............." },
  { "name": "toggle_reg", "wave": "0.1............." },
  { "name": "clk_slow",   "wave": "p...p...p...p..." },
  { "name": "sync1",      "wave": "0...1..........." },
  { "name": "sync2",      "wave": "0.......1......." },
  { "name": "sync3",      "wave": "0...........1..." },
  { "name": "pulse_out",  "wave": "0.......1...0..." }
], "head": { "text": "Transferring a fast pulse across domains using a toggle and detect strategy." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk_fast | input | 1 | Source clock domain; fast positive-edge triggered clock | | rst_fast_n | input | 1 | Asynchronous active-low reset for the fast clock domain | | pulse_in | input | 1 | Single-cycle pulse in the clk_fast domain | | clk_slow | input | 1 | Destination clock domain; slow positive-edge triggered clock | | rst_slow_n | input | 1 | Asynchronous active-low reset for the slow clock domain | | pulse_out | output | 1 | Recreated single-cycle pulse in the clk_slow domain |

Constraints

The fast domain logic must only be clocked by clk_fast and reset by rst_fast_n.
The slow domain logic must only be clocked by clk_slow and reset by rst_slow_n.
The design must use a 2-stage flip-flop synchronizer in the slow domain to capture the toggle signal to resolve metastability.
The output pulse_out must be combinational, derived directly from the synchronized signals, so it asserts on the same clk_slow cycle that the toggle edge is detected.

Topics

togglesynchronizercdcpulse

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