Shift Register Based Delay Line Crossing
Source synchronous interfaces transmit a clock alongside the data. When the clock and data edges are perfectly aligned at the receiver pins, the clock must be artificially delayed to center its active edge within the data valid window. Digital delay lines using tapped shift registers provide a programmable mechanism to achieve this phase shift, allowing the system to adapt to different routing delays and operating conditions.
The module implements a tapped shift register that delays an incoming data signal by a selectable number of clock cycles. A programmable selection input determines which tap of the shift register drives the output. A delay selection of zero bypasses the flip-flops entirely, routing the input directly to the output.
The circuit operates on a positive-edge triggered clock (clk) and uses an asynchronous active-low reset (rst_n). On reset, all shift register stages are cleared to 0. The output data_out is combinational with respect to delay_sel and data_in (when bypass is selected). When delay_sel is greater than zero, the output reflects the state of the corresponding shift register stage.
Worked Trace: Cycle 1: rst_n=0, data_in=1, delay_sel=1 → shift_reg=000, data_out=0 Cycle 2: rst_n=1, data_in=1, delay_sel=1 → shift_reg=000, data_out=0 Cycle 3: rst_n=1, data_in=0, delay_sel=1 → shift_reg=001, data_out=1 Cycle 4: rst_n=1, data_in=1, delay_sel=0 → shift_reg=010, data_out=1 (combinational bypass)
{ "signal": [
{ "name": "clk", "wave": "p......." },
{ "name": "rst_n", "wave": "01......" },
{ "name": "data_in", "wave": "1.0.1.0." },
{ "name": "delay_sel", "wave": "=======.", "data": ["1", "1", "1", "0", "2", "2", "2"] },
{},
{ "name": "shift_reg[0]", "wave": "0.1.0.1." },
{ "name": "shift_reg[1]", "wave": "0..1.0.1" },
{ "name": "data_out", "wave": "0.1.0.1." }
], "head": { "text": "Delay line operation showing dynamic tap selection." } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; clears all shift register stages to 0 | | data_in | input | 1 | Serial data input | | delay_sel| input | 2 | Selects the delay in clock cycles (0 to 3) | | data_out | output | 1 | Delayed data output |
Constraints
- Positive-edge triggered clock and asynchronous active-low reset.
- All shift register stages must reset to
0. data_outmust immediately reflect changes todelay_selordata_in(whendelay_selis0) without waiting for a clock edge.- Maximum delay supported is 3 clock cycles.
Topics
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