FIFO Depth with Different Read and Write Rates
Asynchronous FIFOs absorb data bursts between clock domains with mismatched throughputs and differing clock frequencies. The system under analysis transfers a burst of B data items from a source domain to a destination domain.
The source clock operates at f_wr and writes data continuously for 3 out of every 4 clock cycles. The destination clock operates at f_rd and can only read data 1 out of every 2 clock cycles.
Calculate the required FIFO depth to prevent overflow during a maximum burst transfer under various clock frequency ratios.
Constraints
- The burst size
Brepresents the total number of items written before the source pauses. - The source writes exactly 3 items per 4
clk_wrcycles during the burst. - The destination reads exactly 1 item per 2
clk_rdcycles whenever the FIFO is not empty. - Required depth must be rounded up to the nearest integer.
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