FSM with Synchronous and Asynchronous Resets

Complex control systems often require multiple tiers of reset. A full system power cycle triggers an asynchronous hard reset to completely initialize the hardware, while a software-triggered watchdog might issue a synchronous soft reset to abort the current operation and restart the sequence without dropping system links.

The state machine in this module manages a simple processing sequence. It waits in an IDLE state until a start signal is received. Once started, it transitions to a RESTART phase, then automatically enters a PROCESS phase on the next cycle, where it waits for a done signal. Upon completion, it enters a FINISH phase before returning to IDLE on the following cycle.

Two reset mechanisms govern this FSM. An asynchronous active-low reset (rst_n) forces the FSM into the IDLE state immediately. A synchronous active-high soft reset (soft_rst) forces the FSM into the RESTART state on the next clock edge, aborting any current operation. The active output is asserted during the RESTART and PROCESS states.

Timing and Reset Rules: • Clock edge: posedge clk. • Reset 1: rst_n is an asynchronous, active-low hard reset. When asserted, state_out immediately becomes 3'b000 (IDLE) and active becomes 0. • Reset 2: soft_rst is a synchronous, active-high soft reset. When asserted (and rst_n is high), the state transitions to 3'b001 (RESTART) on the next clock edge. • Priority: rst_n has the highest priority. soft_rst has the second-highest priority and overrides all other state transitions (e.g., start or done). • State Encodings: IDLE = 3'b000, RESTART = 3'b001, PROCESS = 3'b010, FINISH = 3'b011. • Outputs: state_out is a registered output representing the current state. active is a combinational output that evaluates to 1 only when the current state is RESTART or PROCESS.

Worked Trace: Cycle 1: rst_n=0, soft_rst=0 → state_out=0 (IDLE), active=0 Cycle 2: rst_n=1, start=1 → state_out=1 (RESTART), active=1 Cycle 3: start=0 → state_out=2 (PROCESS), active=1 Cycle 4: done=0 → state_out=2 (PROCESS), active=1 (hold) Cycle 5: soft_rst=1 → state_out=1 (RESTART), active=1 (soft reset overrides hold) Cycle 6: soft_rst=0, rst_n=0 → state_out=0 (IDLE), active=0 (async reset overrides soft reset)

flowchart LR
    RESET(( )) -->|rst_n=0| IDLE
    IDLE((IDLE)) -->|start=1| RESTART
    IDLE -->|start=0| IDLE
    RESTART(["RESTART ★"]):::out -->|unconditional| PROCESS
    PROCESS(["PROCESS ★"]):::out -->|done=1| FINISH
    PROCESS -->|done=0| PROCESS
    FINISH((FINISH)) -->|unconditional| IDLE
    classDef out fill:#6C5CE7,stroke:#5B4FE8,color:#fff

{ "signal": [
  { "name": "clk",      "wave": "p........" },
  { "name": "rst_n",    "wave": "01......0" },
  { "name": "soft_rst", "wave": "0...10..." },
  { "name": "start",    "wave": "010......" },
  { "name": "done",     "wave": "0.....10." },
  {},
  { "name": "state_out","wave": "=========", "data": ["0", "0", "1", "2", "2", "1", "2", "3", "0"] },
  { "name": "active",   "wave": "001111100" }
], "head": { "text": "FSM trace showing normal operation, soft reset interruption, and async reset." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low hard reset; forces state_out to 3'b000 | | soft_rst | input | 1 | Synchronous active-high soft reset; forces state_out to 3'b001 | | start | input | 1 | Active-high start signal | | done | input | 1 | Active-high done signal | | state_out | output | 3 | Current state of the FSM | | active | output | 1 | Combinational output; 1 when state is RESTART or PROCESS |

Constraints

• Clock edge and reset polarity must be strictly observed.
• rst_n must take priority over soft_rst.
• soft_rst must take priority over all other state transitions.
• state_out must be a registered output matching the internal FSM state.
• active must be a combinational output that updates immediately when the state changes.
• State encodings must exactly match the specification: IDLE = 3'b000, RESTART = 3'b001, PROCESS = 3'b010, FINISH = 3'b011.

Topics

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