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Codiode/Problems/Sequential Logic

Gated SR Latch: Transparency Window Trace

EasyLogic CircuitTiming Diagram

A gated SR latch passes the state of its inputs to the output immediately as long as the enable signal is HIGH, and holds its current state when the enable signal is LOW.

Four signals are shown: EN (enable), S (set input), R (reset input) and Q (output, initially 0).

Trace Q across all 10 time steps.

Constraints

  • S and R are never HIGH at the same time.
  • Q updates immediately when EN is HIGH and holds its value when EN is LOW.

Topics

latchessequential-logictiming-diagram

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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

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