Hold Margin Calculation with Skew
High-speed digital designs often fail post-silicon validation because clock routing delays create timing mismatches between communicating flip-flops.
The schematic displays two flip-flops, FF1 (launch) and FF2 (capture), connected by a combinational logic path. The timing parameters for the standard cells are t_pcq = 2, t_comb_min = 0, and t_hold = 1. The clock network introduces a clock skew of t_skew = 1.5. The clock edge arrives at FF2 1.5 time units after it arrives at FF1. Positive skew helps setup time but actively hurts hold time by delaying the closing of the capture window.
Determine the hold margin at FF2 and identify the minimum combinational delay required to resolve any timing violations.
Constraints
- All timing values are in nominal time units (e.g., nanoseconds).
- Hold margin is defined as the difference between the fastest data arrival time and the required hold time at the capture flop.
- Negative hold margin indicates a timing violation.
Topics
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