JK Flip-Flop from a D Flip-Flop
The JK flip-flop is a universal sequential element — it subsumes the behavior of SR, D, and T flip-flops through its four operating modes. It is named for Jack Kilby, who developed early semiconductor memory, and appears frequently in interview questions because it tests the candidate's understanding of all flip-flop types and their interrelationships. In modern ASIC design, JK flip-flops are synthesized from D flip-flops using combinational logic on the D input.
Your task is to implement a JK flip-flop using one DFF, two AND gates, two NOT gates, and one OR gate (6 components total). The JK flip-flop has two control inputs J and K, and behaves on each positive clock edge as follows:
J=0, K=0 → Q_next = Q (hold current state) J=1, K=0 → Q_next = 1 (set) J=0, K=1 → Q_next = 0 (reset) J=1, K=1 → Q_next = NOT(Q) (toggle)
The conversion equation is: D = J AND NOT(Q) OR NOT(K) AND Q. This maps all four JK modes onto the DFF's D input. The J term sets Q when Q is currently 0. The NOT(K) term holds Q when K=0, or clears the path when K=1.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | J | input | 1 | J input: when J=1 and K=0, Q is set to 1 on the next clock edge | | K | input | 1 | K input: when J=0 and K=1, Q is reset to 0 on the next clock edge | | CLK | input | 1 | Clock, positive-edge triggered | | Q | output | 1 | Flip-flop state output |
Constraints
- Use exactly 1 DFF, 2 AND gates, 2 NOT gates, and 1 OR gate (6 components total).
- The Q output of the DFF feeds back into the combinational logic — two NOT/AND paths use Q as an input.
- No forbidden state exists in a JK flip-flop: J=K=1 toggles Q and is fully valid.
- Q transitions occur on the positive edge of CLK only.
Topics
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