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Codiode/Problems/Sequential Logic

JK Master-Slave: 1s-Catching Problem

HardLogic CircuitTiming Diagram

A pulse-triggered master-slave JK flip-flop captures any logic 1 on its inputs while CLK is HIGH and transfers the captured state to the output on the HIGH-to-LOW transition of CLK.

Four signals are shown: CLK (clock, period 4), J (input), K (input), and Q (output, initially 0).

Trace Q across all 16 time steps.

Constraints

  • The master latch evaluates J and K continuously while CLK is 1.
  • Any logic 1 on J or K during the HIGH phase of CLK is caught and cannot be undone until the next clock cycle.
  • The output Q only changes state exactly at the HIGH-to-LOW falling edge of CLK.

Topics

master-slavesequential-logictiming-diagramflip-flops

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