JK Flip-Flop vs SR Forbidden State
A positive-edge-triggered JK flip-flop toggles its output when both inputs are HIGH, whereas a positive-edge-triggered SR flip-flop enters an indeterminate state when both inputs are HIGH. Five signals are shown: CLK (clock, period 2), IN1 (shared J and S input), IN2 (shared K and R input), Q_JK (JK output, initially 0), and Q_SR (SR output, initially 0). Trace Q_JK and Q_SR across all 12 time steps.
Constraints
- Evaluate input signals only on the LOW-to-HIGH transitions of
CLK. - Use the character "X" to represent an indeterminate state for any output.
- Mid-cycle input changes do not affect the output until the next rising clock edge.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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