Missing Synchronization on Static Register
A configuration register provides a software-controlled enable signal to a high-speed hardware processing block. The SwEnable signal dictates whether the fast domain logic processes incoming data or remains idle.
Expected behavior:
When SwEnable transitions, the fast domain should safely register the new state without metastability. The internal Active signal should reflect the state of SwEnable after a safe synchronization delay.
Simulation reports intermittent setup and hold violations on the fast domain control registers when SwEnable is toggled. The output Active occasionally enters an undefined state during the clock cycle immediately following a software update. Inspect the circuit and correct the fault.
Constraints
- You must use D flip-flops to synchronize the asynchronous input.
- The synchronizer must be clocked by
FastClk. - Do not modify the downstream logic block or the source register.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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