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Codiode/Problems/Sequential Logic

Multiple Driver Resolution Failure

MediumLogic CircuitDebug

A shared internal data bus routes data from multiple peripheral registers to a central processor core.

Expected behavior:

| sel_a | sel_b | data_a | data_b | bus_out | |---------|---------|----------|----------|-----------| | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | 0 | | 0 | 1 | 0 | 1 | 1 | | 0 | 1 | 1 | 0 | 0 | | 1 | 0 | 1 | 0 | 1 | | 1 | 0 | 0 | 1 | 0 | | 1 | 1 | 1 | 0 | 1 | | 1 | 1 | 0 | 1 | 0 |

Compilation fails with a multiple-driver error on the bus_out signal. The test bench cannot simulate the design because the strict single-driver rule for the logic data type is violated. Inspect the circuit and correct the fault.

Constraints

  • Do not change the module port list.
  • Drive the output using a single multiplexed data path.
  • sel_a takes priority over sel_b if both are asserted simultaneously.

Topics

MultiplexerData PathSystemVerilogRTL

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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

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