Pessimistic vs Optimistic Flag Generation
Asynchronous FIFOs rely on synchronized read and write pointers to safely generate full and empty flags across independent clock domains.
The design under analysis is a 16-deep FIFO utilizing 5-bit Gray code pointers: wr_ptr in the write domain and rd_ptr in the read domain. The full flag is evaluated exclusively in the write domain by comparing wr_ptr against the synchronized read pointer rd_ptr_sync. The empty flag is evaluated in the read domain by comparing rd_ptr against the synchronized write pointer wr_ptr_sync. Synchronization requires a standard two-flop synchronizer, introducing a two-cycle latency.
Determine the exact state of the flags during simultaneous read and write bursts. Prove mathematically whether the flag generation logic evaluates available space optimistically or pessimistically and identify the system-level consequences of this evaluation.
Constraints
- Synchronization latency is exactly 2 clock cycles in the destination domain.
- The FIFO depth is 16 entries.
- Pointers are 5 bits wide to distinguish between full and empty conditions.
- Gray code is used for all pointer domain crossings.
Topics
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