Pipelined Multiply Accumulate Unit
Digital Signal Processing (DSP) algorithms, like FIR filters and neural network accelerators, rely heavily on Multiply-Accumulate (MAC) units. To achieve high clock frequencies, the critical path through the multiplier and adder must be broken up. Pipelining the MAC unit allows new data to be ingested every clock cycle, but it requires precise synchronization of control signals to ensure the accumulator feeds back exactly when the product is ready.
The module receives 8-bit unsigned inputs a and b, along with a valid_in flag and a clr_acc flag. It processes these inputs through a 3-stage pipeline. Stage 1 registers the inputs. Stage 2 computes and registers the 16-bit product. Stage 3 adds the product to the 32-bit accumulator and registers the result. The clr_acc signal must travel down the pipeline alongside the data; when it reaches Stage 3, the accumulator overwrites its current value with the new product instead of adding to it. If valid_in is low, invalid bubbles propagate through the pipeline, meaning valid_out will be low 3 cycles later, and the accumulator will hold its state without adding anything.
- Clock edge:
posedge clk - Reset type: Asynchronous, active-low
rst_n - Reset behavior: All internal pipeline registers, validity flags, and the accumulator reset to 0.
- Priority rules: If
valid_inis 0, the pipeline shifts in a bubble, ignoringclr_acc,a, andb. The accumulator must not update or clear when a bubble reaches Stage 3.
Cycle 1: rst_n=0 → acc_out=0, valid_out=0
Cycle 2: rst_n=1, valid_in=1, clr_acc=1, a=2, b=3 → acc_out=0, valid_out=0 (Stage 1 registers inputs)
Cycle 3: valid_in=1, clr_acc=0, a=4, b=5 → acc_out=0, valid_out=0 (Stage 2 registers product 6)
Cycle 4: valid_in=0, clr_acc=0, a=0, b=0 → acc_out=0, valid_out=0 (Stage 3 is still empty)
Cycle 5: valid_in=0 → acc_out=6, valid_out=1 (Stage 3 loads 6 because clr_acc=1 reached the end)
Cycle 6: valid_in=0 → acc_out=26, valid_out=1 (Stage 3 adds product 20 to accumulator 6)
Cycle 7: valid_in=0 → acc_out=26, valid_out=0 (Bubble reaches Stage 3, accumulator holds){ "signal": [
{ "name": "clk", "wave": "p......." },
{ "name": "rst_n", "wave": "01......" },
{ "name": "valid_in", "wave": "0110...." },
{ "name": "clr_acc", "wave": "0100...." },
{ "name": "a", "wave": "22222222", "data": ["0","2","4","0","0","0","0","0"] },
{ "name": "b", "wave": "22222222", "data": ["0","3","5","0","0","0","0","0"] },
{},
{ "name": "valid_out", "wave": "0...110." },
{ "name": "acc_out", "wave": "22222222", "data": ["0","0","0","0","6","26","26","26"] }
], "head": { "text": "Pipeline latency of 3 cycles for valid data and clear signals." } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; all registers go to 0 when asserted | | valid_in | input | 1 | When 1, a, b, and clr_acc are accepted into the pipeline | | clr_acc | input | 1 | When 1 (and valid_in is 1), the accumulator resets to the new product instead of adding | | a | input | 8 | First unsigned operand | | b | input | 8 | Second unsigned operand | | valid_out | output | 1 | High when acc_out contains a newly updated valid accumulation | | acc_out | output | 32 | Current value of the accumulator register |
Constraints
- Clock edge is
posedge clk. - Reset is asynchronous, active-low
rst_n. - All pipeline registers, validity flags, and the accumulator must reset to 0.
- Pipeline latency must be exactly 3 cycles from input to output.
- The accumulator must not update or clear when the
valid_insignal for that specific operation was 0. - The
clr_accsignal must be delayed to match the data pipeline so it clears the accumulator at the exact moment the corresponding product arrives.
Topics
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