Reconvergent Paths with Different Latencies

High-speed digital signal processing pipelines often branch data into parallel paths with different computational latencies. When these paths reconverge, the designer must manually align the data using delay lines to ensure the correct operands are combined.

The module receives an 8-bit input data_in alongside a valid_in control signal. The data splits into two parallel paths. The computation path applies a three-stage mathematical operation: it adds 12 to the input in the first stage, multiplies the result by 3 in the second stage, and subtracts 5 in the third stage. The bypass path simply carries the original data_in value. In the fourth and final stage, the result of the computation path is added to the original data_in value from the bypass path. Because the computation takes three clock cycles, the bypass path must use a delay line to hold the original input so it arrives at the final adder at the exact same time as the computed result. The final sum is registered and output on data_out.

Clock and Reset Rules: • Clock edge: posedge clk • Reset type: Asynchronous, active-low (rst_n) • Reset behavior: All internal pipeline registers, delay line registers, valid_out, and data_out must reset to 0. • Pipeline progression: Data advances through the pipeline every clock cycle. valid_out must be asserted exactly 4 cycles after valid_in is asserted, and it must propagate through the pipeline stages alongside the data.

Worked Trace: Cycle 1: rst_n=0 → valid_out=0, data_out=0 Cycle 2: rst_n=1, valid_in=1, data_in=10 → Inputs sampled at end of cycle. Cycle 3: valid_in=0 → Stage 1 computes 10 + 12 = 22; delay line stage 1 holds 10. Cycle 4: valid_in=0 → Stage 2 computes 22 * 3 = 66; delay line stage 2 holds 10. Cycle 5: valid_in=0 → Stage 3 computes 66 - 5 = 61; delay line stage 3 holds 10. Cycle 6: valid_in=0 → Final stage computes 61 + 10 = 71; valid_out=1, data_out=71.

{ "signal": [
  { "name": "clk",       "wave": "p........" },
  { "name": "rst_n",     "wave": "01......." },
  { "name": "valid_in",  "wave": "010......" },
  { "name": "data_in",   "wave": "0=0......", "data": ["10"] },
  {},
  { "name": "valid_out", "wave": "0....10.." },
  { "name": "data_out",  "wave": "0....=0..", "data": ["71"] }
], "head": { "text": "Four-cycle latency for computation and reconvergence." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; clears all registers to 0 | | valid_in | input | 1 | Indicates data_in is valid and should be processed | | data_in | input | 8 | Input data payload | | valid_out | output | 1 | Indicates data_out is valid; delayed exactly 4 cycles from valid_in | | data_out | output | 8 | Final registered result of the reconverged paths |

Constraints

• All internal pipeline registers and outputs must be updated on the positive edge of clk.
• All registers must be asynchronously cleared to 0 when rst_n is 0.
• All intermediate calculations and the final sum must use 8-bit arithmetic; overflows wrap around naturally.
• The valid_in signal must strictly shift through a 4-cycle delay line to become valid_out.
• If valid_out is 0, the value of data_out is considered a don't care by the downstream system, but for deterministic behavior it must reflect the continuous operation of the pipeline.

Topics

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