Global Pipeline Stall

High-performance processors rely on pipelined datapaths to maximize throughput. When a pipeline encounters a multi-cycle operation or a cache miss, it must pause execution. A global stall mechanism freezes the entire pipeline simultaneously, ensuring no in-flight data or control signals are overwritten or lost while waiting for the bottleneck to clear.

This module is a 3-stage pipeline that propagates an 8-bit data payload and a 1-bit valid flag. Under normal operation, data and valid signals advance to the next stage on every clock cycle, creating a 3-cycle latency from input to output. When the global stall signal is asserted, all three stages hold their current state. The inputs presented during a stalled cycle are ignored unless they are held until the stall is de-asserted.

The module uses a positive-edge triggered clock clk and a synchronous active-low reset rst_n. On reset, all valid bits and data registers (both internal and output) must clear to 0. The reset signal has the highest priority; if rst_n is 0, the pipeline clears regardless of the stall signal.

Cycle 1: rst_n=0, stall=0, v_in=1, d_in=255 → v_out=0, d_out=0 (Reset) Cycle 2: rst_n=1, stall=0, v_in=1, d_in=170 → v_out=0, d_out=0 (Stage 1 loads 170) Cycle 3: rst_n=1, stall=0, v_in=0, d_in=0 → v_out=0, d_out=0 (Stage 2 loads 170) Cycle 4: rst_n=1, stall=1, v_in=0, d_in=0 → v_out=0, d_out=0 (Stall! Pipeline holds) Cycle 5: rst_n=1, stall=0, v_in=0, d_in=0 → v_out=1, d_out=170 (Stage 3 loads 170) Cycle 6: rst_n=1, stall=0, v_in=0, d_in=0 → v_out=0, d_out=0 (Pipeline clears)

{ "signal": [
  { "name": "clk",   "wave": "p....." },
  { "name": "rst_n", "wave": "01...." },
  { "name": "stall", "wave": "0..10." },
  { "name": "v_in",  "wave": "1.0..." },
  { "name": "d_in",  "wave": "======", "data": ["255", "170", "0", "0", "0", "0"] },
  {},
  { "name": "v_out", "wave": "0...10" },
  { "name": "d_out", "wave": "======", "data": ["0", "0", "0", "0", "170", "0"] }
], "head": { "text": "Pipeline propagating a single valid byte, interrupted by a 1-cycle stall." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Synchronous active-low reset. Clears all internal valid and data registers to 0. | | stall | input | 1 | Global stall. When 1, all pipeline stages hold their current state. | | v_in | input | 1 | Valid bit for incoming data | | d_in | input | 8 | Incoming data payload | | v_out | output | 1 | Valid bit for outgoing data (Stage 3) | | d_out | output | 8 | Outgoing data payload (Stage 3) |

Constraints

• Clock edge and reset: clk is posedge, rst_n is synchronous active-low.
• Reset values: All valid bits and data registers (both internal and output) must clear to 0 on reset.
• Pipeline depth: The module must implement exactly 3 stages of latency.
• Priority: Reset has the highest priority. If rst_n is 0, the pipeline clears regardless of the stall signal.
• Stall behavior: When stall is 1, no data advances. Inputs presented during a stalled cycle are ignored unless they are held until the stall is de-asserted.

Topics

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