Ring Counter: Self-Correction for All-Zeros Lockup
Uninitialized shift registers power up in unpredictable states. A standard ring counter initialized to all zeros will lock up permanently, producing no control sequence for the rest of the system.
Implement a 4-bit ring counter with synchronous self-correction. The circuit must detect the invalid 0000 state and force the counter into the valid 1000 state on the next clock cycle. When the input rst is 1, the counter must synchronously clear all outputs to 0. When rst is 0, the counter shifts right, with Q0 feeding back to Q3. If the all-zeros state occurs, the detection logic must override the standard feedback to inject a 1 into Q3.
| rst | Current State (Q3 Q2 Q1 Q0) | Next State (Q3 Q2 Q1 Q0) | |-------|-------------------------------------|----------------------------------| | 1 | Any | 0 0 0 0 | | 0 | 0 0 0 0 | 1 0 0 0 | | 0 | 1 0 0 0 | 0 1 0 0 | | 0 | 0 1 0 0 | 0 0 1 0 | | 0 | 0 0 1 0 | 0 0 0 1 | | 0 | 0 0 0 1 | 1 0 0 0 |
Constraints
- Implement using exactly four D flip-flops.
- Use a 4-input NOR gate to detect the all-zeros condition.
- All state transitions and resets must be synchronous to the clock.
- Do not use asynchronous preset or clear pins on the flip-flops.
Topics
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