Ripple Counter: Q2 Stuck-at-0 Fault Debug
A 4-bit ripple counter generates a sequential binary count from 0 to 15 on each clock pulse.
Expected behavior:
| CLK pulses | Q3 | Q2 | Q1 | Q0 | |--------------|------|------|------|------| | 0 | 0 | 0 | 0 | 0 | | 1 | 0 | 0 | 0 | 1 | | 2 | 0 | 0 | 1 | 0 | | 3 | 0 | 0 | 1 | 1 | | 4 | 0 | 1 | 0 | 0 | | 5 | 0 | 1 | 0 | 1 | | 6 | 0 | 1 | 1 | 0 | | 7 | 0 | 1 | 1 | 1 | | 8 | 1 | 0 | 0 | 0 |
Simulation shows the count sequence jumps incorrectly. After reaching 3 (0011), the next clock cycle produces 0 (0000) instead of 4 (0100). The observed decimal sequence is 0, 1, 2, 3, 8, 9, 10, 11. Bit Q2 remains permanently at 0, while Q3 continues to toggle correctly.
Inspect the circuit and correct the fault.
Constraints
- Do not add new flip-flops or replace the entire counter architecture.
- You may only modify wiring, connections, or fixed logic levels driving the existing flip-flops.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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